Inventor
BUEHLER MARKUS T
DE4 patents
Patents
4 patentsUS7308669B2Dec 11, 2007
Use of redundant routes to increase the yield and reliability of a VLSI layout
IBM211 citations98
US8380737B2Feb 19, 2013
Computing intersection of sets of numbers
IBM2 citations56
US7962881B2Jun 14, 2011
Via structure to improve routing of wires within an integrated circuit
IBM2 citations52
US7398485B2Jul 8, 2008
Yield optimization in router for systematic defects
IBM0 citations41