Inventor

BROWN JEFFREY S

US84 patents

⚠️ This page may combine multiple inventors who share the name “BROWN JEFFREY S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BROWN JEFFREY S

IBM

Concurrent Fin-FET and thick-body device fabrication

Method of forming a semiconductor diode with depleted polysilicon gate structure

Method and structure to process thick and thin fins and variable fin to fin spacing

High voltage N-LDMOS transistors having shallow trench isolation region

Depleted polysilicon circuit element and method for producing the same

Semiconductor diode with depleted polysilicon gate structure and method

Method and structure to process thick and thin fins and variable fin to fin spacing

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby

Process for buried diode formation in CMOS

Integrated antifuse structure for FINFET and CMOS devices

Method for increasing latch-up immunity in CMOS devices

Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions

Conductive coupling of electrical structures to a semiconductor device located under a buried oxide layer

Method for producing a polysilicon circuit element

ESD protection structure and method

Method of making a depleted poly-silicon edged MOSFET structure

Depleted poly-silicon edged MOSFET structure and method

Structure and process for buried diode formation in CMOS

DRAM cell with enhanced SER immunity

Method and structure for increasing the threshold voltage of a corner device

Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby

Method and structure to reduce latch-up using edge implants

Semiconductor structure and system for fabricating an integrated circuit chip

Voltage detection circuit and circuit for generating a trigger flag signal

DRAM cell with enhanced SER immunity

Zero Threshold Voltage pFET and method of making same

Structure for scalable, low-cost polysilicon DRAM in a planar capacitor

MOSFET with decoupled halo before extension

Transistor having raised source and drain

Method for forming a liner in a trench

Selective silicide blocking

Selective silicide blocking

MOSFET with decoupled halo before extension

INNOVATIVE MAG DRIVE LLC

Containment member for a magnetic-drive centrifugal pump

Corrosion-resistant impeller for a magnetic-drive centrifugal pump

Secondary containment for a magnetic-drive centrifugal pump

Method for forming a corrosion-resistant impeller for a magnetic-drive centrifugal pump

Corrosion-resistant rotor for a magnetic-drive centrifugal pump

INNOVATIVE MAG DRIVE L L C

Centrifugal pump having an axial thrust balancing system

Wear ring assembly for a centrifugal pump

Centrifugal pump having an axial thrust balancing system

LSI LOGIC CORP

Self-timing circuit for semiconductor memory devices

Hard macro having an antenna rule violation free input/output ports

Supply degradation compensation for memory self time circuits

LSI CORP

Cell library management for power optimization

Energy efficient memory access technique for single ended bit cells

ANSIMAG INC

Shaft for a magnetic-drive centrifugal pump using a plurality of grooves

TURNER MARK F

Power grid optimization

BROWN JEFFREY S

Granular channel width for power optimization