Inventor
HOLMES STEVEN J
US286 patents
Patents
50 patentsUS8004024B2Aug 23, 2011
Field effect transistor
IBM106 citations99
US7528494B2May 5, 2009
Accessible chip stack and process of manufacturing thereof
IBM258 citations99
US7351648B2Apr 1, 2008
Methods for forming uniform lithographic features
IBM163 citations99
US7084060B1Aug 1, 2006
Forming capping layer over metal wire structure using selective atomic layer deposition
IBM637 citations99
US6440801B1Aug 27, 2002
Structure for folded architecture pillar memory cell
IBM199 citations99
US6114725ASep 5, 2000
Structure for folded architecture pillar memory cell
IBM160 citations99
US6096598AAug 1, 2000
Method for forming pillar memory cells and device formed thereby
IBM200 citations99
US5945707AAug 31, 1999
DRAM cell with grooved transfer device
IBM127 citations99
US4808511AFeb 28, 1989
Vapor phase photoresist silylation process
IBM165 citations99
US7362412B2Apr 22, 2008
Method and apparatus for cleaning a semiconductor substrate in an immersion lithography system
IBM62 citations98
US6387783B1May 14, 2002
Methods of T-gate fabrication using a hybrid resist
IBM134 citations98
US6221562B1Apr 24, 2001
Resist image reversal by means of spun-on-glass
IBM113 citations98
US8853085B1Oct 7, 2014
Grapho-epitaxy DSA process with dimension control of template pattern
IBM47 citations97
US6506660B2Jan 14, 2003
Semiconductor with nanoscale features
IBM101 citations97
US6184151B1Feb 6, 2001
Method for forming cornered images on a substrate and photomask formed thereby
IBM92 citations97
US6627477B1Sep 30, 2003
Method of assembling a plurality of semiconductor devices having different thickness
IBM68 citations96
US6531724B1Mar 11, 2003
Borderless gate structures
IBM37 citations96
US6429045B1Aug 6, 2002
Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage
IBM74 citations96
US6358813B1Mar 19, 2002
Method for increasing the capacitance of a semiconductor capacitors
IBM56 citations96
US6342735B1Jan 29, 2002
Dual use alignment aid
IBM84 citations96
US6338934B1Jan 15, 2002
Hybrid resist based on photo acid/photo base blending
IBM126 citations96
US6121651ASep 19, 2000
Dram cell with three-sided-gate transfer device
IBM68 citations96
US6114082ASep 5, 2000
Frequency doubling hybrid photoresist having negative and positive tone components and method of preparing the same
IBM81 citations96
US6110653AAug 29, 2000
Acid sensitive ARC and method of use
IBM72 citations96
US6037194AMar 14, 2000
Method for making a DRAM cell with grooved transfer device
IBM82 citations96
US6007968ADec 28, 1999
Method for forming features using frequency doubling hybrid resist and device formed thereby
IBM47 citations96
US5998835ADec 7, 1999
High performance MOSFET device with raised source and drain
IBM50 citations96
US5981148ANov 9, 1999
Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby
IBM49 citations96
US5882967AMar 16, 1999
Process for buried diode formation in CMOS
IBM49 citations96
US5776660AJul 7, 1998
Fabrication method for high-capacitance storage node structures
IBM64 citations96
US7256415B2Aug 14, 2007
Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells
IBM49 citations95
US6190988B1Feb 20, 2001
Method for a controlled bottle trench for a dram storage node
IBM64 citations95
US6147394ANov 14, 2000
Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby
IBM54 citations95
US5959325ASep 28, 1999
Method for forming cornered images on a substrate and photomask formed thereby
IBM43 citations95
US8492274B2Jul 23, 2013
Metal alloy cap integration
IBM19 citations93
US7585614B2Sep 8, 2009
Sub-lithographic imaging techniques and processes
IBM28 citations93
US7459013B2Dec 2, 2008
Chemical and particulate filters containing chemically modified carbon nanotube structures
IBM23 citations93
US7358120B2Apr 15, 2008
Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM
IBM25 citations93
US7352607B2Apr 1, 2008
Non-volatile switching and memory devices using vertical nanotubes
IBM21 citations93
US7351666B2Apr 1, 2008
Layout and process to contact sub-lithographic structures
IBM36 citations93
US7265013B2Sep 4, 2007
Sidewall image transfer (SIT) technologies
IBM25 citations93
US7233071B2Jun 19, 2007
Low-k dielectric layer based upon carbon nanostructures
IBM33 citations93
US7071047B1Jul 4, 2006
Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions
IBM19 citations93
US6995065B2Feb 7, 2006
Selective post-doping of gate structures by means of selective oxide growth
IBM15 citations93
US6846727B2Jan 25, 2005
Patterned SOI by oxygen implantation and annealing
IBM29 citations93
US6596597B2Jul 22, 2003
Method of manufacturing dual gate logic devices
IBM18 citations93
US6489207B2Dec 3, 2002
Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor
IBM38 citations93
US6372412B1Apr 16, 2002
Method of producing an integrated circuit chip using frequency doubling hybrid photoresist and apparatus formed thereby
IBM16 citations93
US6333229B1Dec 25, 2001
Method for manufacturing a field effect transitor (FET) having mis-aligned-gate structure
IBM42 citations93
US6333533B1Dec 25, 2001
Trench storage DRAM cell with vertical three-sided transfer device
IBM20 citations93
Showing the top 50 of 286 patents by PatentIndex Score.