Inventor

LEIDY ROBERT K

US95 patents

⚠️ This page may combine multiple inventors who share the name “LEIDY ROBERT K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEIDY ROBERT K

IBM

CMOS imager array with recessed dielectric

Damascene copper wiring image sensor

Method for forming cornered images on a substrate and photomask formed thereby

Wafer chuck having a removable insert

Antifuse structure and process

Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby

Process for buried diode formation in CMOS

Embedded power and ground plane structure

Antifuse structure

Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby

Method for forming cornered images on a substrate and photomask formed thereby

Nested overlay measurement target

CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom

Image sensor including spatially different active and dark pixel interconnect patterns

Stacked imager package

Stacked imager package

CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom

ESD protection structure and method

Structure and process for buried diode formation in CMOS

Process for enhanced lithographic imaging

Fabricating a floating gate with field enhancement feature self-aligned to a groove

Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby

Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby

Method and structure to reduce latch-up using edge implants

Electrical test structure and method for space and line measurement

Structure for reducing microelectronic short circuits using spin-on glass as part of the interlayer dielectric

Integrated waveguide structure with perforated chip edge seal

Bipolar junction transistors with reduced base-collector junction capacitance

Bipolar junction transistors with reduced base-collector junction capacitance

Delamination and crack resistant image sensor structures and methods

Pixel sensor having doped isolation structure sidewall

Transistor having raised source and drain

Method and system for determining overlay tolerance

Method for improving visibility of alignment targets in semiconductor processing

Method for forming transistors with raised source and drains and device formed thereby

Pixel sensor having doped isolation structure sidewall

Damascene resistor and method for measuring the width of same

Reverse tone process for masks

Method for forming transistors with raised source and drains and device formed thereby

Method and structure to reduce latch-up using edge implants

Method and structure to reduce latch-up using edge implants

Method for improving visibility of alignment target in semiconductor processing

Dual bond pad structure for photonics

Dual bond pad structure for photonics

ADKISSON JAMES W

Tunable filter structures and design structures

Self-dicing chips using through silicon vias

GLOBALFOUNDRIES INC

Multi-chip modules with vertically aligned grating couplers for transmission of light signals between optical waveguides

Barrier structures for underfill blockout regions

GAMBINO JEFFREY P

Methods of forming self-aligned through silicon via

INTERNAT BUSINESS MACHIENS COR

Damascene copper wiring optical image sensor