Inventor
DURHAM CHRISTOPHER MCCALL
US36 patents
⚠️ This page may combine multiple inventors who share the name “DURHAM CHRISTOPHER MCCALL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
35 patentsUS6785826B1Aug 31, 2004
Self power audit and control circuitry for microprocessor functional units
IBM111 citations98
US6522170B1Feb 18, 2003
Self-timed CMOS static logic circuit
IBM35 citations93
US5964866AOct 12, 1999
Elastic self-timed interface for data flow elements embodied as selective bypass of stages in an asynchronous microprocessor pipeline
IBM22 citations93
US5896059AApr 20, 1999
Decoupling capacitor fuse system
IBM20 citations93
US5761517AJun 2, 1998
System and method for reducing power consumption in high frequency clocked circuits
IBM40 citations93
US5737614AApr 7, 1998
Dynamic control of power consumption in self-timed circuits
IBM32 citations93
US6147508ANov 14, 2000
Power consumption control mechanism and method therefor
IBM48 citations92
US5896046AApr 20, 1999
Latch structure for ripple domino logic
IBM32 citations92
US5870411AFeb 9, 1999
Method and system for testing self-timed circuitry
IBM37 citations92
US6532574B1Mar 11, 2003
Post-manufacture signal delay adjustment to solve noise-induced delay variations
IBM47 citations91
US6240489B1May 29, 2001
Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system
IBM28 citations91
US6208907B1Mar 27, 2001
Domino to static circuit technique
IBM30 citations91
US6189133B1Feb 13, 2001
Coupling noise reduction technique using reset timing
IBM38 citations91
US6000036ADec 7, 1999
Logical steering to avoid hot spots on integrated circuits
IBM43 citations90
US6507929B1Jan 14, 2003
System and method for diagnosing and repairing errors in complementary logic
IBM14 citations84
US6107852AAug 22, 2000
Method and device for the reduction of latch insertion delay
IBM16 citations83
US5708374AJan 13, 1998
Self-timed control circuit for self-resetting logic circuitry
IBM16 citations82
US6577152B1Jun 10, 2003
Noise suppression circuit for suppressing above-ground noises
IBM8 citations74
US6181156B1Jan 30, 2001
Noise suppression circuits for suppressing noises above and below reference voltages
IBM14 citations74
US5790560AAug 4, 1998
Apparatus and method for timing self-timed circuitry
IBM8 citations74
US6406980B1Jun 18, 2002
Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets
IBM8 citations73
US6253350B1Jun 26, 2001
Method and system for detecting errors within complementary logic circuits
IBM14 citations73
US6209055B1Mar 27, 2001
Method and apparatus for reducing noise induced among conductive lines
IBM10 citations73
US5912900AJun 15, 1999
Method and system for testing self-timed circuitry
IBM11 citations73
US6269045B1Jul 31, 2001
Self-timed address decoder for register file and compare circuit of multi-port cam
IBM4 citations71
US6072746AJun 6, 2000
Self-timed address decoder for register file and compare circuit of a multi-port CAM
IBM5 citations71
US6252418B1Jun 26, 2001
Reduced area active above-supply and below-ground noise suppression circuits
IBM12 citations69
US6049230AApr 11, 2000
Silicon on insulator domino logic circuits
IBM10 citations68
US6150834ANov 21, 2000
Elimination of SOI parasitic bipolar effect
IBM4 citations63
US6133758AOct 17, 2000
Selectable self-timed replacement for self-resetting circuitry
IBM6 citations63
US6654937B1Nov 25, 2003
Register file timing using static timing tools
IBM4 citations62
US6115789ASep 5, 2000
Method and system for determining which memory locations have been accessed in a self timed cache architecture
IBM6 citations61
US6195308B1Feb 27, 2001
Self-timed address decoder for register file and compare circuit of a multi-port cam
IBM1 citations60
US6285217B1Sep 4, 2001
Dynamic logic circuits with reduced evaluation time
IBM0 citations52
US6037804AMar 14, 2000
Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs
IBM0 citations51