Inventor
GILLETT JR RICHARD B
US22 patents
⚠️ This page may combine multiple inventors who share the name “GILLETT JR RICHARD B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
DIGITAL EQUIPMENT CORP
18 patentsUS6049889AApr 11, 2000
High performance recoverable communication method and apparatus for write-only networks
DIGITAL EQUIPMENT CORP125 citations96
US4937733AJun 26, 1990
Method and apparatus for assuring adequate access to system resources by processors in a multiprocessor computer system
DIGITAL EQUIPMENT CORP69 citations96
US4858116AAug 15, 1989
Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
DIGITAL EQUIPMENT CORP75 citations96
US5426741AJun 20, 1995
Bus event monitor
DIGITAL EQUIPMENT CORP96 citations94
US5829051AOct 27, 1998
Apparatus and method for intelligent multiple-probe cache allocation
DIGITAL EQUIPMENT CORP33 citations92
US5111424AMay 5, 1992
Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfer
DIGITAL EQUIPMENT CORP28 citations92
US5068781ANov 26, 1991
Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
DIGITAL EQUIPMENT CORP37 citations92
US5034883AJul 23, 1991
Lockhead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
DIGITAL EQUIPMENT CORP41 citations92
US5003467AMar 26, 1991
Node adapted for backplane bus with default control
DIGITAL EQUIPMENT CORP52 citations92
US4980854ADec 25, 1990
Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
DIGITAL EQUIPMENT CORP38 citations92
US4949239AAug 14, 1990
System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
DIGITAL EQUIPMENT CORP46 citations92
US4947368AAug 7, 1990
Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
DIGITAL EQUIPMENT CORP23 citations92
US4941083AJul 10, 1990
Method and apparatus for initiating interlock read transactions on a multiprocessor computer system
DIGITAL EQUIPMENT CORP29 citations92
US4774422ASep 27, 1988
High speed low pin count bus interface
DIGITAL EQUIPMENT CORP33 citations92
US5341510AAug 23, 1994
Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor
DIGITAL EQUIPMENT CORP12 citations74
US5146563ASep 8, 1992
Node with coupling resistor for limiting current flow through driver during overlap condition
DIGITAL EQUIPMENT CORP14 citations73
US4837736AJun 6, 1989
Backplane bus with default control
DIGITAL EQUIPMENT CORP9 citations73
US4829515AMay 9, 1989
High performance low pin count bus interface
DIGITAL EQUIPMENT CORP14 citations73