Inventor

MCBRIDE JOHN G

US39 patents

⚠️ This page may combine multiple inventors who share the name “MCBRIDE JOHN G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCBRIDE JOHN G

HEWLETT PACKARD CO

Speed optimal bit ordering in a cache memory

Method and system for estimating capacitive coupling in a hierarchical design

Method and apparatus for determining the RC delays of a network of an integrated circuit

System and method for approximating the coupling voltage noise on a node

Programmable disk array controller having n counters for n disk drives for stripping data where each counter addresses specific memory location by a count n

Method and system for screening a VLSI design for inductive coupling noise

Timing consistent dynamic compare with force miss circuit

Speed efficient cache output selector circuitry based on tag compare and data organization

Method and apparatus for determining which branch of a network of an integrated circuit has the largest total effective RC delay

Method and apparatus for determining the maximum permitted and minimum required width of a feedback FET on a precharge node

Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit

Method and apparatus for determining certain characteristics of circuit elements

System and method for evaluating the loading of a clock driver

System and method for detecting multiplexers in a circuit design

System and method for propagating clock nodes in a netlist of circuit design

System and method for detecting NFETs that pull up to VDD and PFETs that pull down to ground

System and method for detecting FETs that are susceptible to bootstrapping

System and method for detecting pass FETs

System and method for detecting NOR gates and NAND gates

Framework for rules checking

Electrical rules checker system and method for reporting problems with tri-state logic in electrical rules checking

Electrical rules checker system and method providing quality assurance of tri-state logic

System and method for detecting an excessive number of series-connected pass FETs

System and method for detecting storage nodes that are susceptible to charge sharing

System and method for detecting the output of a clock driver

Method and apparatus for generating a database which is used for determining the design quality of network nodes

Evaluation of the design quality of network nodes

Three purpose shadow register attached to the output of storage devices

System and method for evaluating a very large scale integrated circuit for potential design errors

Framework for rules checking utilizing resistor, nonresistor, node and small node data structures

HEWLETT PACKARD DEVELOPMENT CO

Method and apparatus for evaluating the design quality of network nodes

Method and apparatus for evaluating the design quality of network nodes

System and method for executing tests on an integrated circuit design

Method and apparatus for prioritizing the order in which checks are performed on a node in an integrated circuit

Electrical rules checker system and method using tri-state logic for electrical rule checks

Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit

System and method for detecting nodes that are susceptible to floating

Method and apparatus for determining whether an element in an integrated circuit is a feedback element

Method and apparatus for evaluating the design quality of network nodes