Inventor

YANG MING-TZONG

TW97 patents

⚠️ This page may combine multiple inventors who share the name “YANG MING-TZONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YANG MING-TZONG

UNITED MICROELECTRONICS CORP

Method of automatically generating dummy metals for multilevel interconnection

Method forming shallow trench isolation

Process for fabricating a stacked capacitor

Multiple well device and process of manufacture

Single bit erase flash EEPROM

Method of thinning for EEPROM tunneling oxide device

Method of fabrication of MOSFET device with buried bit line

Process for producing memory devices having narrow buried N+ lines

Method of fabricating electrically erasable read only memory cell

Symmetric SRAM cell with buried N+ local interconnection line

Multilayer ONO structure

Active layer mask with dummy pattern

Multiple cell with common bit line contact and method of manufacture thereof

Method of manufacture of pull down transistor with drain off-set for low leakage SRAM&#39;s

Method of making high coupling ratio NAND type flash memory

SOI by large angle oxygen implant

Method of manufacture of semiconductor memory device with multiple, orthogonally disposed conductors

Double rim phase shifter mask

Metal via sidewall tilt angle implant for SOG

Process for fabricating a stacked capacitor

Method for fabricating semiconductor device isolation using double oxide spacers

Method of forming a stacked capacitor using sidewall spacers and local oxidation

Process for fabricating double poly high density buried bit line mask ROM

Dram capacitor structure

Process for forming an FET read only memory device

Electrically erasable read only memory cell array having elongated control gate in a trench

Memory cell fabricated by floating gate structure

Method of forming MOSFET devices with buried bitline capacitors

Drain off-set for pull down transistor for low leakage SRAM&#39;s

Method of making single bit erase flash EEPROM

Method for forming increased density for interconnection metallization

Single polysilicon neuron MOSFET

Neuron MOSFET with different interpolysilicon oxide

Self aligning fabrication method for sub-resolution phase shift mask

Single layer thin film transistor static random access memory cell

Double poly high density buried bit line mask ROM

Split polysilicon SRAM cell

Double destruction phase shift mask

Sealed vacuum electronic devices

Method for forming a metallurgy system having a dielectric layer that is planar and void free

MEDIATEK INC

Lateral bipolar junction transistor with reduced base resistance

Seal ring structure with capacitor

Semiconductor package assemblies with system-on-chip (SOC) packages

Semiconductor package structure and method for forming the same

Semiconductor package with through silicon via interconnect

Lateral bipolar junction transistor

Semiconductor package assembly with through silicon via interconnect

SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect

KO CHING-CHUNG

Integrated inductor

HUNG CHENG-CHOU

Seal ring structure with capacitor

Method of manufacture of pull down transistor with drain off-set for low leakage SRAM's

Drain off-set for pull down transistor for low leakage SRAM's