Inventor

MADAN SUDHIR K

US36 patents

⚠️ This page may combine multiple inventors who share the name “MADAN SUDHIR K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MADAN SUDHIR K

TEXAS INSTRUMENTS INC

Low voltage, low power static random access memory cell

Trench isolation structure and method for forming

Method and apparatus for reducing leakage current in an SRAM array

Ferroelectric memory cell with access transmission gate

Compact memory circuit

Low voltage, low power static random access memory cell

Trench isolation structure having a trench formed in a LOCOS structure and a channel stop region on the sidewalls of the trench

Circuit and method for reducing access transistor gate oxide stress

Apparatus and method for static random access memory array

Single sided bit line restore for power reduction

Plateline driver for a ferroelectric memory

Memory with 6T small aspect ratio cells having metal—1 elements physically connected to metal—0 elements

Bitline precharge timing scheme to improve signal margin

Reference voltage generator for ferroelectric memory

Microelectronic device with centered storage capacitor cavity sized less than feature size

Method of forming a microelectronic contact

Scrambling method to reduce wordline coupling noise

Stacked DRAM structure

Method of forming a microelectronic device having a cavity smaller than lithographic tolerances

Stable source-coupled sense amplifier

Method for memory sensing

Memory cell with reduced coupling between pass transistor and drive transistor bodies and method

Method of making stacked DRAM capacitor structure by using a conformal conductor

Intermediate structure for forming a storage capacitor

Low-power redundancy for non-volatile memory

Plateline driver with RAMP rate control

Sense amplifier with override write circuitry

Ferroelectric memory devices with partitioned platelines

MADAN SUDHIR K

Method of reading a ferroelectric memory cell

Data path read/write sequencing for reduced power consumption

High reliability and low power redundancy for memory

Method to maintain power supply voltage during brownout

Memory array power domain partitioning

MOTOROLA INC

Local interconnect for stacked polysilicon device

Method of forming layered polysilicon filled contact by doping sensitive endpoint etching

Method for making a polysilicon transistor