Inventor

YOO CHUE-SAN

TW61 patents

⚠️ This page may combine multiple inventors who share the name “YOO CHUE-SAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YOO CHUE-SAN

TAIWAN SEMICONDUCTOR MFG

Pseudo silicon on insulator MOSFET device

Pseudo silicon on insulator MOSFET device

Reduction of the aspect ratio of deep contact holes for embedded DRAM devices

Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer

Method of making dual isolation regions for logic and embedded memory devices

Protective film for fuse window passivation for semiconductor integrated circuit applications

Method of forming a highly transparent silicon rich nitride protective layer for a fuse window

Method of using disposable hard mask for gate critical dimension control

Multiple tilted angle ion implantation MOSFET method

Peeling free metal silicide films using rapid thermal anneal

Tapered opening sidewall with multi-step etching process

Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure

Using oxide junction to cut off sub-threshold leakage in CMOS devices

Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure

Planarization process using tailored etchback and CMP

Integration of SAC and salicide processes by combining hard mask and poly definition

Method of making a semiconductor device having 4t sram and mixed-mode capacitor in logic

Method for forming vias in multi-level integrated circuits, for use with multi-level metallizations

Method of making a semiconductor device having high density 4T SRAM in logic with salicide process

Fabrication method for integrating logic and single level polysilicon DRAM devices on the same semiconductor chip

Method for using disposable hard mask for gate critical dimension control

Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells

Integrated Ti-W polycide for deep submicron processing

Method of forming salicided self-aligned contact for SRAM cells

Critical dimension control with a planarized underlayer

Polycide gate MOSFET process for integrated circuits

Integrated circuit having an opening for a fuse

Method of making an integrated circuit having an opening for a fuse

Peeling free metal silicide films using ion implantation

Contact sidewall tapering with argon sputtering

Method of forming a shallow trench isolation that has rounded and protected corners

Method of making an improved field oxide isolation structure for semiconductor integrated circuits having higher field oxide threshold voltages

Logic and single level polysilicon DRAM devices fabricated on the same semiconductor chip

Two-step planer field oxidation method

Forming a semi-recessed metal for better EM and Planarization using a silo mask

Method of manufacture of SRAM with SIPOS resistor

Self-aligned phase shifter formation

Method for making improved capacitors on dynamic random access memory having increased capacitance, longer refresh times, and improved yields

Capping free metal silicide integrated process

Photomask haze reduction via ventilation

Method of making an improved field oxide isolation structure for semiconductor integrated circuits having higher field oxide threshold voltages

TAIWAN SEMICONDUCTOR MFG CO LTD

Pellicle removal method

Apparatus and a method of forming a particle shield

Pellicle having vent hole

Pellicle and method of using the same

Pellicle and method of using the same

Apparatus and a method of forming a particle shield

Pellicle and method of using the same

Pattern transfer technique and method of manufacturing the same

LIN CHENG-MING

Mask and blank storage inner gas