Inventor

RYAN CHARLES P

US32 patents

⚠️ This page may combine multiple inventors who share the name “RYAN CHARLES P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RYAN CHARLES P

BULL HN INFORMATION SYST

Apparatus for synchronizing multiple processors in a data processing system

Controlling cache predictive prefetching based on cache hit ratio trend

Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack

Data processing system processor dynamic selection of internal signal tracing

Pipelined central processor managing the execution of instructions with proximate successive branches in a cache-based data processing system while performing block mode transfer predictions

Controllably operable method and apparatus for predicting addresses of future operand requests by examination of addresses of prior cache misses

Cache miss prediction method and apparatus for use with a paged main memory in a data processing system

Synchronization of branch cache searches and allocation/modification/deletion of branch cache

Method and apparatus for determining CC-NUMA intra-processor delays

Unknown response processing in a diagnostic expert system

Method and apparatus for exhaustively testing interactions among multiple processors

High integrity cache directory

Method and system for cache miss prediction based on previous cache access requests

Gateword acquisition in a multiprocessor write-into-cache environment

Balanced access to prevent gateword dominance in a multiprocessor write-into-cache environment

Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords

Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment

HONEYWELL INF SYSTEMS

Cache memory command buffer circuit

Verification of real page numbers of stack stored prefetched instructions from instruction cache

Cache with independent addressable data and directory arrays

Instruction buffer associated with a cache memory unit

Apparatus for cache clearing

Data processing system programmable pre-read capability

Cache unit information replacement apparatus

Cache apparatus for enabling overlap of instruction fetch operations

Cache unit with transit block buffer apparatus

Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands

Program switching monitor

(unassigned)

Data processing system processor delay instruction

Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor

HONEYWELL BULL

Prioritized secondary use of a cache with simultaneous access

BULL INFORMATION SYSTEMS INC

Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio