Inventor

SHELLY WILLIAM A

US35 patents

⚠️ This page may combine multiple inventors who share the name “SHELLY WILLIAM A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHELLY WILLIAM A

BULL HN INFORMATION SYST

Apparatus for synchronizing multiple processors in a data processing system

Data processing system processor dynamic selection of internal signal tracing

Fault tolerant multiprocessor computer system

Method and apparatus for exhaustively testing interactions among multiple processors

Calendar clock caching in a multiprocessor data processing system

Information block transfer management in a multiprocessor computer system employing private caches for individual center processor units and a shared cache

Private cache miss and access management in a multiprocessor system with shared memory

High integrity cache directory

Gate close balking for fair gating in a nonuniform memory architecture data processing system

Binary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unit

Safestore frame implementation in a central processor

Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable data

Central processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor count

Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count

Basic operations synchronization and local mode controller in a VLSI central processor

Computer processor read/alter/rewrite optimization cache invalidate signals

Data processing system utilizing multiple resister loading for fast domain switching

Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment

HONEYWELL INF SYSTEMS

Central processor

Instruction buffer associated with a cache memory unit

Data processing system programmable pre-read capability

Cache arrangement utilizing a split cycle mode of operation

Cache unit with transit block buffer apparatus

Programmable interface apparatus and method

Method and apparatus for prefetching instructions for a central execution pipeline unit

Dual validity bit arrays

Cache arrangement for performing simultaneous read/write operations

Steering code generating apparatus for use in an input/output processing system

Processor for input-output processing system

Memory steering in a data processing system

BULL INFORMATION SYSTEMS INC

Error detection in the basic processing unit of a VLSI central processor

Gate close failure notification for fair gating in a nonuniform memory architecture data processing system

(unassigned)

Data processing system processor delay instruction

WILHITE JOHN E

Method and apparatus for initiating the execution of instructions using a central pipeline execution unit

HONEYWELL BULL

Distributor of machine words between units of a central processor