Inventor
OGURA TOMOKO
US50 patents
⚠️ This page may combine multiple inventors who share the name “OGURA TOMOKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HALO LSI INC
32 patentsUS6670240B2Dec 30, 2003
Twin NAND device structure, array operations and fabrication method
HALO LSI INC124 citations99
US6807105B2Oct 19, 2004
Fast program to program verify method
HALO LSI INC27 citations96
US6549463B2Apr 15, 2003
Fast program to program verify method
HALO LSI INC31 citations96
US6914791B1Jul 5, 2005
High efficiency triple well charge pump circuit
HALO LSI INC78 citations95
US7031192B1Apr 18, 2006
Non-volatile semiconductor memory and driving method
HALO LSI INC46 citations93
US7006378B1Feb 28, 2006
Array architecture and operation methods for a nonvolatile memory
HALO LSI INC31 citations93
US6999345B1Feb 14, 2006
Method of sense and program verify without a reference cell for non-volatile semiconductor memory
HALO LSI INC35 citations93
US6825084B2Nov 30, 2004
Twin NAND device structure, array operations and fabrication method
HALO LSI INC25 citations93
US6759290B2Jul 6, 2004
Stitch and select implementation in twin MONOS array
HALO LSI INC31 citations93
US6714456B1Mar 30, 2004
Process for making and programming and operating a dual-bit multi-level ballistic flash memory
HALO LSI INC24 citations93
US6631088B2Oct 7, 2003
Twin MONOS array metal bit organization and single cell operation
HALO LSI INC24 citations93
US6567314B1May 20, 2003
Data programming implementation for high efficiency CHE injection
HALO LSI INC25 citations93
US6542412B2Apr 1, 2003
Process for making and programming and operating a dual-bit multi-level ballistic flash memory
HALO LSI INC26 citations93
US6459622B1Oct 1, 2002
Twin MONOS memory cell usage for wide program
HALO LSI INC50 citations93
US6643172B2Nov 4, 2003
Bit line decoding scheme and circuit for dual bit memory with a dual bit selection
HALO LSI INC13 citations84
US6636438B2Oct 21, 2003
Control gate decoder for twin MONOS memory with two bit erase capability
HALO LSI INC13 citations84
US6631089B1Oct 7, 2003
Bit line decoding scheme and circuit for dual bit memory array
HALO LSI INC15 citations84
US7352033B2Apr 1, 2008
Twin MONOS array for high speed application
HALO LSI INC8 citations74
US7046553B2May 16, 2006
Fast program to program verify method
HALO LSI INC4 citations74
US6636439B1Oct 21, 2003
Fast program to program verify method
HALO LSI INC4 citations74
US6628546B2Sep 30, 2003
Fast program to program verify method
HALO LSI INC4 citations74
US9123419B2Sep 1, 2015
Complementary reference method for high reliability trap-type non-volatile memory
HALO LSI INC2 citations63
US7936604B2May 3, 2011
High speed operation method for twin MONOS metal bit array
HALO LSI INC4 citations63
US7447077B2Nov 4, 2008
Referencing scheme for trap memory
HALO LSI INC2 citations63
US7118961B2Oct 10, 2006
Stitch and select implementation in twin MONOS array
HALO LSI INC3 citations63
US6998658B2Feb 14, 2006
Twin NAND device structure, array operations and fabrication method
HALO LSI INC1 citations63
US6856545B2Feb 15, 2005
Fast program to program verify method
HALO LSI INC2 citations63
US6628547B2Sep 30, 2003
Fast program to program verify method
HALO LSI INC2 citations63
US8027198B2Sep 27, 2011
Trap-charge non-volatile switch connector for programmable logic
HALO LSI INC0 citations52
US8023326B2Sep 20, 2011
Trap-charge non-volatile switch connector for programmable logic
HALO LSI INC0 citations52
US7190603B2Mar 13, 2007
Nonvolatile memory array organization and usage
HALO LSI INC0 citations52
US6611461B2Aug 26, 2003
Fast program to program verify method
HALO LSI INC0 citations52
HALO LSI DESIGN & DEVICE TECH
6 patentsUS6177318B1Jan 23, 2001
Integration method for sidewall split gate monos transistor
HALO LSI DESIGN & DEVICE TECH198 citations99
US6133098AOct 17, 2000
Process for making and programming and operating a dual-bit multi-level ballistic flash memory
HALO LSI DESIGN & DEVICE TECH251 citations99
US6477088B2Nov 5, 2002
Usage of word voltage assistance in twin MONOS cell during program and erase
HALO LSI DESIGN & DEVICE TECH56 citations96
US6248633B1Jun 19, 2001
Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
HALO LSI DESIGN & DEVICE TECH347 citations96
US6038169AMar 14, 2000
Read reference scheme for flash memory
HALO LSI DESIGN & DEVICE TECH24 citations93
US6002611ADec 14, 1999
Fast, low current program with auto-program for flash memory
HALO LSI DESIGN & DEVICE TECH8 citations74
OGURA TOMOKO
3 patentsUS8139410B2Mar 20, 2012
Trap-charge non-volatile switch connector for programmable logic
OGURA TOMOKO5 citations72
US8174885B2May 8, 2012
High speed operation method for twin MONOS metal bit array
OGURA TOMOKO0 citations50
US8089809B2Jan 3, 2012
Trap-charge non-volatile switch connector for programmable logic
OGURA TOMOKO0 citations50
HALO LSI DEVICE & DESIGN TECHN
2 patentsUS6366500B1Apr 2, 2002
Process for making and programming and operating a dual-bit multi-level ballistic flash memory
HALO LSI DEVICE & DESIGN TECHN37 citations96
US6359807B1Mar 19, 2002
Process for making and programming and operating a dual-bit multi-level ballistic flash memory
HALO LSI DEVICE & DESIGN TECHN32 citations92