Inventor

PRAMANICK SHEKHAR

US61 patents

⚠️ This page may combine multiple inventors who share the name “PRAMANICK SHEKHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PRAMANICK SHEKHAR

ADVANCED MICRO DEVICES INC

Transistor with local insulator structure

Method of manufacturing a transistor with local insulator structure

Manufacturing method for semiconductor metalization barrier

Method of fabricating an integrated circuit having punch-through suppression

Semiconductor metalization barrier

Method for electrically conductive metal-to-metal bonding

Copper interconnect with improved electromigration resistance

Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile

Method for forming low dielectric passivation of copper interconnects

Copper interconnect methodology for enhanced electromigration resistance

Self-aligned semiconductor interconnect barrier and manufacturing method therefor

Method of forming reliable capped copper interconnects

Method of forming reliable capped copper interconnects

Dual barrier and conductor deposition in a dual damascene process for semiconductors

Copper metalization with improved electromigration resistance

Method of forming reliable copper interconnects

Low resistance salicide technology with reduced silicon consumption

Method of reliably capping copper interconnects

Semiconductor interconnect barrier for fluorinated dielectrics

Self-aligned silicide gate technology for advanced submicron MOS devices

Prevention of inter-channel current leakage in semiconductors

Low resistance composite contact structure utilizing a reaction barrier layer under a metal layer

Formation of low thermal budget shallow abrupt junctions for semiconductor devices

Alloy barrier layers for semiconductors

Method and system for modifying and densifying a porous film

Chemical-mechanical polishing of semiconductors

Low energy passivation of conductive material in damascene process for semiconductors

Semiconductor device having an intermetallic layer on metal interconnects

Low resistance metal contact technology

Method for implanting semiconductor conductive layers

Transistor with local insulator structure

Elevated salicide technology

Elevated source/drain salicide CMOS technology

T-shaped gate device and method for making

Electron bean curing of low-k dielectrics in integrated circuits

Dual barrier and conductor deposition in a dual damascene process for semiconductors

Semiconductor interconnect interface processing by pulse laser anneal

Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure

Pad structure for copper interconnection and its formation

Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant

End-of-range damage suppression for ultra-shallow junction formation

Ultra shallow junction formation using amorphous silicon layer

Virtual hard mask for etching

Method of forming shallow junctions by entrapment of interstitial atoms

Void detection in metallization patterns

Semiconductor interconnect barrier and manufacturing method thereof

High density plasma oxide gap filled patterned metal layers with improved electromigration resistance

Self-aligned SOI device with body contact and NiSi2 gate

Barrier materials for metal interconnect in a semiconductor device

(unassigned)

Method for making multilayered coaxial interconnect structure