Inventor

AJIT JANARDHANAN S

US63 patents

⚠️ This page may combine multiple inventors who share the name “AJIT JANARDHANAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AJIT JANARDHANAN S

BROADCOM CORP

Sub-micron high input voltage tolerant input output (I/O) circuit

Sub-micron high input voltage tolerant input output (I/O) circuit

I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off

Delay circuit and method with delay relatively independent of process, voltage, and temperature variations

System and method utilizing a one-stage level shift circuit

I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off

Methods and systems for sensing and compensating for process, voltage, temperature, and load variations

Methods and systems for sensing and compensating for process, voltage, temperature, and load variations

Delay circuit with delay relatively independent of process, voltage, and temperature variations

Methods and systems for reducing power-on failure of integrated circuits

Method utilizing a one-stage level shift circuit

System and method for compensating for the effects of process, voltage, and temperature variations in a circuit

Sub-micron high input voltage tolerant input output (I/O) circuit

Sub-micron high input voltage tolerant input output (I/O) circuit

Sub-micron high input voltage tolerant input output (I/O) circuit

Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations

Methods and systems for reducing power-on failure of integrated circuits

Delay circuit and method with delay relatively independent of process, voltage, and temperature variations

Methods and systems for providing load-adaptive output current drive

INT RECTIFIER CORP

SiC semiconductor device

Trench depletion MOSFET

Termination structure for mosgated device with reduced mask count and process for its manufacture

Emitter-switched transistor structures

Base resistance controlled thyristor structure with high-density layout for increased current capacity

Reduced mask process for manufacture of MOS gated devices using dopant-enhanced-oxidation of semiconductor

Bidirectional thyristor with MOS turn-off capability with a single gate

Emitter switched thyristor

Three-terminal MOS-gate controlled thyristor structures with current saturation characteristics

Bidirectional thyristor with MOS turn-on and turn-off capability

MOS-gated power semiconductor devices with conductivity modulation by positive feedback mechanism

Bidirectional thyristor with MOS turn-off capability with a single gate

Reduced mask process for manufacture of MOS gated devices

High band gap layer to isolate wells in high voltage power integrated circuits

MOS-controlled thyristor with current saturation characteristics

Three-terminal thyristor with single MOS-gate controlled characteristics

POWER INTEGRATIONS INC

High-voltage transistor with multi-layer conduction region

High-voltage transistor with multi-layer conduction region

Method of making a high-voltage transistor with multiple lateral conduction layers

High-voltage transistor with multi-layer conduction region

High-voltage transistor with multi-layer conduction region

Method of making a high-voltage transistor with buried conduction regions

High-voltage transistor with multi-layer conduction region

High-voltage transistor with multi-layer conduction region

Method of making a high-voltage transistor with buried conduction regions

High-voltage transistor with multi-layer conduction region

High-voltage transistor with multi-layer conduction region

EXAR CORP

ESD structure for IC with over-voltage capability at pad in steady-state

Over-voltage tolerant integrated circuit I/O buffer

Slew-rate-control structure for high-frequency operation

Low-power integrated circuit I/O buffer