Inventor

TRAN LUAN

US57 patents

⚠️ This page may combine multiple inventors who share the name “TRAN LUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRAN LUAN

MICRON TECHNOLOGY INC

Method for integrated circuit fabrication using pitch multiplication

Pitch reduced patterns relative to photolithography features

Methods for increasing photo alignment margins

Memory cell arrays

Method for integrated circuit fabrication using pitch multiplication

Pitch reduced patterns relative to photolithography features

Method for integrated circuit fabrication using pitch multiplication

Integrated circuit device having non-linear active area pillars

Methods of forming integrated circuitry, and methods of forming dynamic random access memory circuitry

Depletion compensated polysilicon electrodes

Method of making a semiconductor device having improved contacts to a thin conductive layer

Methods for increasing photo-alignment margins

Methods for increasing photo-alignment margins

Memory cell arrays comprising intersecting slanted portions

Method for integrated circuit fabrication using pitch multiplication

High density access transistor having increased channel width and methods of fabricating such devices

High density memory array having increased channel widths

Selective polysilicon stud growth

Selective polysilicon stud growth

Memory integrated circuitry with DRAMs using LOCOS isolations and areas less than 6F2

Selective polysilicon stud growth

Semiconductor device having improved contacts to a thin conductive layer

Methods for increasing photo alignment margins

Compound structure for reduced contact resistance

Method of making memory cell arrays

Semiconductor devices including fine pitch arrays with staggered contacts

High density memory array having increased channel widths

Word lines for memory cells

Compound structure for reduced contact resistance

Compound structure for reduced contact resistance

Selective polysilicon stud growth

Method of forming integrated circuitry

Selective polysilicon stud growth

Depletion compensated polysilicon electrodes

Method of making a semiconductor device having improved contacts

Method of making a semiconductor device having improved contacts

High density memory devices having improved channel widths and cell size

Selective polysilicon stud growth

Selective polysilicon stud growth

Methods of providing ohmic contact

TRAN LUAN

Integrated circuit having pitch reduced patterns relative to photoithography features

Pitch reduced patterns relative to photolithography features

Pitch reduced patterns relative to photolithography features

ROUND ROCK RES LLC

Pitch reduced patterns relative to photolithography features

Structures with increased photo-alignment margins

Pitch reduced patterns relative to photolithography features

(unassigned)

Selective polysilicon stud growth of 6F2 memory cell manufacturing having a convex upper surface profile

ABATCHEV MIRZAFER K

Method for integrated circuit fabrication using pitch multiplication

NEC LAB AMERICA INC

Parking lot surveillance with viewpoint invariant object recognition by synthesization and domain adaptation

DIGITAL EQUIPMENT CORP

Static random access memory having tunable-self-timed control logic circuits