Inventor

INOUE AIICHIRO

JP31 patents

⚠️ This page may combine multiple inventors who share the name “INOUE AIICHIRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INOUE AIICHIRO

FUJITSU LTD

Pre-prefetching target of following branch instruction based on past history

Branch instruction execution control apparatus

Detection of overwrite modification by preceding instruction possibility of fetched instruction code using fetched instructions counter and store target address

Virtual storage address space access control system including auxiliary translation lookaside buffer

Method and apparatus for controlling instruction in pipeline processor

Predicted return address selection upon matching target in branch history table with entries in return address stack

Instruction processing device and method for controlling branch instruction accompanied by mode change

Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof

Program counter control method and processor thereof for controlling simultaneous execution of a plurality of instructions including branch instructions using a branch prediction mechanism and a delay instruction for branching

Instruction controlling system and method thereof

Processor performing parallel operations subject to operand register interference using operand history storage

System and method for serialization control of accesses to a common main storage

Information processing apparatus provided with branch history with plurality of designation ways

Circuit for executing conditional branch instructions in pipeline process

Centralized command transfer control system for connecting processors which independently send and receive commands

Pipeline system branch history table storing branch instruction addresses and target addresses with inhibit bits

Return target address prediction by moving entry pointer to return stack popped at completion to deeper one at return instruction fetch

Memory access device and method using address translation history table

Instruction processing apparatus

Instruction control method and processor to process instructions by out-of-order processing using delay instructions for branching

Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal

Pre-fetch control device, data processing apparatus and pre-fetch control method

Instruction control apparatus and method using micro program

Method and apparatus overcoming delay introduced by instruction interlocking in pipelined instruction execution

Instruction control apparatus for loading plurality of instructions into execution stage

Information processing device enabling floating interrupt to be pending and a method executing an interrupt condition change instruction

Virtual storage address space access control

Instruction execution apparatus comprising a commit stack entry unit

Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions

KOIDE MASATERU

Multi-chip module

SUGIZAKI GO

Information processing apparatus, memory control method, and memory control device utilizing local and global snoop control units to maintain cache coherency