Inventor
LIN ERIC
TW36 patents
⚠️ This page may combine multiple inventors who share the name “LIN ERIC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CONEXANT SYSTEMS INC
5 patentsUS7260066B2Aug 21, 2007
Apparatus for link failure detection on high availability Ethernet backplane
CONEXANT SYSTEMS INC58 citations95
US7813263B2Oct 12, 2010
Method and apparatus providing rapid end-to-end failover in a packet switched communications network
CONEXANT SYSTEMS INC37 citations92
US7760719B2Jul 20, 2010
Combined pipelined classification and address search method and apparatus for switching environments
CONEXANT SYSTEMS INC32 citations90
US7373425B2May 13, 2008
High-speed MAC address search engine
CONEXANT SYSTEMS INC9 citations83
US8356334B2Jan 15, 2013
Data network node having enhanced security features
CONEXANT SYSTEMS INC0 citations40
LOGITECH EUROPE SA
4 patentsUSD954583SJun 14, 2022
Video doorbell device
LOGITECH EUROPE SA25 citations94
USD946442SMar 22, 2022
Video doorbell mount
LOGITECH EUROPE SA16 citations93
USD946443SMar 22, 2022
Video doorbell mount
LOGITECH EUROPE SA15 citations93
USD947705SApr 5, 2022
Chime unit for a video doorbell
LOGITECH EUROPE SA10 citations85
PALANTIR TECHNOLOGIES INC
4 patentsUS10204119B1Feb 12, 2019
Inferring a dataset schema from input files
PALANTIR TECHNOLOGIES INC9 citations82
US10540333B2Jan 21, 2020
Inferring a dataset schema from input files
PALANTIR TECHNOLOGIES INC2 citations71
US12210491B2Jan 28, 2025
Inferring a dataset schema from input files
PALANTIR TECHNOLOGIES INC0 citations61
US11907181B2Feb 20, 2024
Inferring a dataset schema from input files
PALANTIR TECHNOLOGIES INC0 citations61
INTEL CORP
3 patentsUS7634768B2Dec 15, 2009
Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machine
INTEL CORP13 citations83
US7415701B2Aug 19, 2008
Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machine
INTEL CORP11 citations80
US8015557B2Sep 6, 2011
Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machine
INTEL CORP3 citations62