Inventor

BORKENHAGEN JOHN MICHAEL

US53 patents

⚠️ This page may combine multiple inventors who share the name “BORKENHAGEN JOHN MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BORKENHAGEN JOHN MICHAEL

IBM

Method and apparatus for selecting thread switch events in a multithreaded processor

Altering thread priorities in a multithreaded processor

Method and apparatus to force a thread switch in a multithreaded processor

SDRAM address error detection method and apparatus

Thread switch control in a multithreaded processor system

Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor

Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes

Programmable compensated delay for DDR SDRAM interface using programmable delay loop for reference calibration

Data strobe gating for source synchronous communications interface

Method and apparatus for implementing high speed DDR SDRAM read interface with reduced ACLV effects

Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels

Method and stacked memory structure for implementing enhanced cooling of memory devices

Data strobe gating for source synchronous communications interface

Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system

Programmable SRAM and DRAM cache interface with preset access priorities

Method and apparatus for communicating translation command information in a multithreaded environment

System for modifying microprocessor operations independently of the execution unit upon detection of preselected opcodes

Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes

Memory chip for high capacity memory subsystem supporting replication of command data

Memory controller and method for handling DMA operations during a page copy

Shared cache line update mechanism

Memory chip for high capacity memory subsystem supporting multiple speed bus

Handling DMA operations during a page copy

Patrol snooping for higher level cache eviction candidate identification

Independent sequencers in a DRAM control structure

Diagnostic interface architecture for memory device

Method and apparatus to interleave level 1 data cache line fill data between system bus and level 2 data cache for improved processor performance

Dual-mode memory chip for high capacity memory subsystem

High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules

Handling DMA requests in a virtual memory environment

Implementing redundant memory access using multiple controllers on the same bank of memory

Implementing directory organization to selectively optimize performance or reliability

Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces

Memory chip having an apportionable data bus

Self timed memory chip having an apportionable data bus

Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces

Dynamic allocation of shared cache directory for optimizing performance

Diagnostic interface architecture for memory device

Dynamic optimization of latency and bandwidth on DRAM interfaces

Method and apparatus to purge remote node cache lines to support hot node replace in a computing system

Dynamically producing an effective impedance of an output driver with a bounded variation during transitions thereby reducing jitter

Autonomic bus reconfiguration for fault conditions

Hub for supporting high capacity memory subsystem

Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory

Computer system having an apportionable data bus and daisy chained memory chips

Memory system having an apportionable data bus and daisy chained memory chips

Configurable directory allocation

BEN-YEHUDA SHMUEL

Apparatus for and method for real-time optimization of virtual machine input/output performance

BARTLEY GERALD KEITH

Digital data architecture employing redundant links in a daisy chain of component modules

LENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD

Multi-server system interconnect