Inventor

OAKLAND STEVEN F

US41 patents

⚠️ This page may combine multiple inventors who share the name “OAKLAND STEVEN F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OAKLAND STEVEN F

IBM

Method of electrically blowing fuses under control of an on-chip tester interface apparatus

CMOS state saving latch

Clock signal latency elimination network

Clock generator having improved deskewer

Low power LSSD flip flops and a flushable single clock splitter for flip flops

Method for reduced electrical fusing time

Functional frequency testing of integrated circuits

Pipeline array

Microcontroller for logic built-in self test (LBIST)

High performance state saving circuit

Testable bus control logic circuitry and method for using same

Testable passgate logic circuits

Functional frequency testing of integrated circuits

Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility

Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility

Method and apparatus for in-system redundant array repair on integrated circuits

Functional frequency testing of integrated circuits

Method and circuit using boundary scan cells for design library analysis

Method and apparatus for in-system redundant array repair on integrated circuits

Output driver that parks output before going tristate

Reduced circuit, high performance, binary select encoder network

Testing using independently controllable voltage islands

System and methods of balancing scan chains and inserting the balanced-length scan chains into hierarchically designed integrated circuits

Design structure for in-system redundant array repair in integrated circuits

Self test method and device for dynamic voltage screen functionality improvement

Access method for embedded JTAG TAP controller instruction registers

Functional frequency testing of integrated circuits

Method for separating shift and scan paths on scan-only, single port LSSD latches

Verifying partial good voltage island structures

Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures

Method and apparatus for in-system redundant array repair on integrated circuits

Compilable memory structure and test methodology for both ASIC and foundry test environments

GRISE GARY D

Microcontroller for logic built-in self test (LBIST)

Microcontroller for logic built-in self test (LBIST)

GILLIS PAMELA S

Method to test hold path faults using functional clocking

Dense register array for enabling scan out observation of both L1 and L2 latches

INTERNAITONAL BUSINESS MACHINE

Serial input shift register built-in self test circuit for embedded circuits

DITLOW GARY S

Low power, high performance PLA

DEGUISE WAYNE J

Multi-mode testing systems

LACROIX LUKE D

Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures

IYENGAR VIKRAM

Hold transition fault model and test generation method