Inventor
SRIVASTAVA RAJEEV
US13 patents
⚠️ This page may combine multiple inventors who share the name “SRIVASTAVA RAJEEV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
EFABLESS CORP
8 patentsUS10671700B2Jun 2, 2020
Systems and methods for obfuscating a circuit design
EFABLESS CORP16 citations92
US10452802B2Oct 22, 2019
Methods for engineering integrated circuit design and development
EFABLESS CORP12 citations91
US11301609B2Apr 12, 2022
Systems and methods for obfuscating a circuit design
EFABLESS CORP3 citations82
US11182526B2Nov 23, 2021
Methods for engineering integrated circuit design and development
EFABLESS CORP3 citations82
US10437953B2Oct 8, 2019
Systems for engineering integrated circuit design and development
EFABLESS CORP7 citations82
US10423748B2Sep 24, 2019
Systems and methods for obfuscating a circuit design
EFABLESS CORP6 citations82
US11748541B2Sep 5, 2023
Methods for engineering integrated circuit design and development
EFABLESS CORP1 citations71
US11775722B2Oct 3, 2023
Systems and methods for obfuscating a circuit design
EFABLESS CORP0 citations61
CADENCE DESIGN SYSTEMS INC
3 patentsUS7600208B1Oct 6, 2009
Automatic placement of decoupling capacitors
CADENCE DESIGN SYSTEMS INC46 citations89
US7810063B1Oct 5, 2010
Graphical user interface for prototyping early instance density
CADENCE DESIGN SYSTEMS INC21 citations88
US7886238B1Feb 8, 2011
Visual yield analysis of intergrated circuit layouts
CADENCE DESIGN SYSTEMS INC13 citations81