P

Inventor

MILLAR BRUCE

CA38 patents
⚠️ This page may combine multiple inventors who share the name “MILLAR BRUCE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOSAID TECHNOLOGIES INC

26 patents
US7299330B2Nov 20, 2007

High bandwidth memory interface

MOSAID TECHNOLOGIES INC74 citations99
US6779097B2Aug 17, 2004

High bandwidth memory interface

MOSAID TECHNOLOGIES INC90 citations99
US6510503B2Jan 21, 2003

High bandwidth memory interface

MOSAID TECHNOLOGIES INC445 citations99
US6087868AJul 11, 2000

Digital delay locked loop

MOSAID TECHNOLOGIES INC147 citations99
US6337590B1Jan 8, 2002

Digital delay locked loop

MOSAID TECHNOLOGIES INC118 citations98
US7834654B2Nov 16, 2010

Dynamic impedance control for input/output buffers

MOSAID TECHNOLOGIES INC18 citations92
US5652733AJul 29, 1997

Command encoded delayed clock generator

MOSAID TECHNOLOGIES INC32 citations92
US5497115AMar 5, 1996

Flip-flop circuit having low standby power for driving synchronous dynamic random access memory

MOSAID TECHNOLOGIES INC34 citations92
US5870049AFeb 9, 1999

Current mode digital to analog converter

MOSAID TECHNOLOGIES INC80 citations90
US8654573B2Feb 18, 2014

High bandwidth memory interface

MOSAID TECHNOLOGIES INC7 citations84
US8035413B2Oct 11, 2011

Dynamic impedance control for input/output buffers

MOSAID TECHNOLOGIES INC10 citations84
US7889580B2Feb 15, 2011

Memory system having incorrupted strobe signals

MOSAID TECHNOLOGIES INC7 citations84
US7652932B2Jan 26, 2010

Memory system having incorrupted strobe signals

MOSAID TECHNOLOGIES INC8 citations84
US7551012B2Jun 23, 2009

Phase shifting in DLL/PLL

MOSAID TECHNOLOGIES INC9 citations83
US7761831B2Jul 20, 2010

ASIC design using clock and power grid standard cell

MOSAID TECHNOLOGIES INC17 citations78
US7671650B2Mar 2, 2010

Timing vernier using a delay locked loop

MOSAID TECHNOLOGIES INC3 citations74
US7593281B2Sep 22, 2009

Voltage down converter for high speed memory

MOSAID TECHNOLOGIES INC4 citations74
US7391247B2Jun 24, 2008

Timing vernier using a delay locked loop

MOSAID TECHNOLOGIES INC4 citations74
US7248531B2Jul 24, 2007

Voltage down converter for high speed memory

MOSAID TECHNOLOGIES INC5 citations74
US7129760B2Oct 31, 2006

Timing vernier using a delay locked loop

MOSAID TECHNOLOGIES INC6 citations74
US6853231B2Feb 8, 2005

Timing vernier using a delay locked loop

MOSAID TECHNOLOGIES INC8 citations74
US5633607AMay 27, 1997

Edge triggered set-reset flip-flop (SRFF)

MOSAID TECHNOLOGIES INC16 citations74
US8013646B2Sep 6, 2011

Timing vernier using a delay locked loop

MOSAID TECHNOLOGIES INC2 citations63
US7863954B2Jan 4, 2011

Timing vernier using a delay locked loop

MOSAID TECHNOLOGIES INC1 citations63
US7765376B2Jul 27, 2010

Apparatuses for synchronous transfer of information

MOSAID TECHNOLOGIES INC1 citations63
US7038517B2May 2, 2006

Timing vernier using a delay locked loop

MOSAID TECHNOLOGIES INC2 citations63

CONVERSANT INTELLECTUAL PROPERTY MAN INC

3 patents

ADVANCED MEMORY INTERNATIONAL

2 patents

SLDRAM INC

2 patents

GILLINGHAM PETER

2 patents

PYEON HONG BEOM

2 patents

MILLAR BRUCE

1 patent