Inventor

SHROFF MEHUL D

US111 patents

⚠️ This page may combine multiple inventors who share the name “SHROFF MEHUL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHROFF MEHUL D

SHROFF MEHUL D

Non-volatile memory and logic circuit process integration

Non-volatile memory and logic circuit process integration

Logic and non-volatile memory (NVM) integration

Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures

Method for forming a split-gate device

Non-volatile memory (NVM) and logic integration

Device matching tool and methods thereof

Via placement and electronic circuit design processing method and electronic circuit design utilizing same

Isolated capacitors within shallow trench isolation

Method and system for physical verification using network segment current

Systems and methods for determining aging damage for semiconductor devices

Capping layer interface interruption for stress migration mitigation

Method of making a logic transistor and a non-volatile memory (NVM) cell

Multi-layer process-induced damage tracking and remediation

Methods of making logic transistors and non-volatile memory cells

Non-volatile memory (NVM) and logic integration

Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric

Non-volatile memory and logic circuit process integration

FREESCALE SEMICONDUCTOR INC

Method for process integration of non-volatile memory cell transistors with transistors of another type

Method for forming an integrated circuit having a programmable fuse

Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility

Layout modification using multilayer-based constraints

Method of forming inter-level dielectric structures on semiconductor devices

Applications for nanopillar structures

3D device packaging using through-substrate posts

Though-substrate vias (TSVs) and method therefor

Techniques for electromigration stress determination in interconnects of an integrated circuit

Treatment for reduction of line edge roughness

Semiconductor devices with non-volatile memory cells

HALL MARK D

Non-volatile memory cell and logic transistor integration

Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic

Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage

Method for forming a split-gate device

Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic

Incident capacitive sensor

Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique

Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric

Logic transistor and non-volatile memory cell integration

Methods of making multi-state non-volatile memory cells

QUICKLOGIC CORP

Metal-to-metal antifuse with non-conductive diffusion barrier

Method of forming a metal-to-metal antifuse with non-conductive diffusion barrier

Metal-to-metal antifuse having improved barrier layer

Programmable device having antifuses without programmable material edges and/or corners underneath metal

Programmable device having antifuses without programmable material edges and/or corners underneath metal

REBER DOUGLAS M

Method for forming an electrical connection between metal layers

Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules

Method and system for derived layer checking for semiconductor device design

MOTOROLA INC

Semiconductor device and method of formation

DEMIRCAN ERTUGRUL

Techniques for electromigration stress determination in interconnects of an integrated circuit

QUICKLASIC CORP

Metal-to-metal antifuse having improved barrier layer