Inventor
EHRENREICH SEBASTIAN
DE17 patents
⚠️ This page may combine multiple inventors who share the name “EHRENREICH SEBASTIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
13 patentsUS7813163B2Oct 12, 2010
Single-ended read and differential write scheme
IBM20 citations92
US7414904B2Aug 19, 2008
Method for evaluating storage cell design using a wordline timing and cell access detection circuit
IBM22 citations91
US7808856B2Oct 5, 2010
Method to reduce leakage of a SRAM-array
IBM16 citations84
US7636254B2Dec 22, 2009
Wordline booster circuit and method of operating a wordline booster circuit
IBM6 citations73
US8363487B2Jan 29, 2013
Method, system, computer program product, and data processing device for monitoring memory circuits and corresponding integrated circuit
IBM6 citations72
US7755408B2Jul 13, 2010
Redundancy in signal distribution trees
IBM4 citations63
US7336115B2Feb 26, 2008
Redundancy in signal distribution trees
IBM3 citations63
US7921388B2Apr 5, 2011
Wordline booster design structure and method of operating a wordine booster circuit
IBM2 citations62
US7675794B2Mar 9, 2010
Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuit
IBM3 citations61
US7626851B2Dec 1, 2009
Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit
IBM6 citations61
US7558138B1Jul 7, 2009
Bypass circuit for memory arrays
IBM4 citations53
US7535750B2May 19, 2009
Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells
IBM0 citations50
US7564739B2Jul 21, 2009
Storage cell design evaluation circuit including a wordline timing and cell access detection circuit
IBM0 citations46