Inventor

LUN ZHAO

SG21 patents

⚠️ This page may combine multiple inventors who share the name “LUN ZHAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUN ZHAO

GLOBALFOUNDRIES INC

Multi-phase source/drain/gate spacer-epi formation

Multi-layer spacer used in finFET

Uniform gate height for semiconductor structure with N and P type fins

Uniform exposed raised structures for non-planar semiconductor devices

Lithographic stack excluding SiARC and method of using same

Reducing gate expansion after source and drain implant in gate last process

CHARTERED SEMICONDUCTOR MFG

Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension

Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension

Semiconductor device and fabrication method

Integrated circuit system employing selective epitaxial growth technology

Nested and isolated transistors with reduced impedance difference

Shallow low energy ion implantation into pad oxide for improving threshold voltage stability

GLOBALFOUNDRIES SG PTE LTD

Method of manufacture of an integrated circuit system with self-aligned isolation structures

Memory cell structure and method for fabrication thereof

Integrated circuit having a plurality of MOSFET devices

TEO LEE WEE

Capacitor top plate over source/drain to form a 1T memory device

Hybrid orientation substrate with stress layer

IBM

MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same

MISHRA SHAILENDRA

Method of forming shallow trench isolation structures for integrated circuits

SAMSUNG ELECTRONICS CO LTD

Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein

WIDODO JOHNNY

Nested and isolated transistors with reduced impedance difference