Inventor

LAI CHUNG WOH

SG24 patents

⚠️ This page may combine multiple inventors who share the name “LAI CHUNG WOH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAI CHUNG WOH

CHARTERED SEMICONDUCTOR MFG

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Method of cobalt silicidation using an oxide-Titanium interlayer

Composite stress spacer

Thermal stability improvement of CoSi2 film by stuffing in titanium

Spacer-less low-k dielectric processes

Integrated circuit system employing selective epitaxial growth technology

Nested and isolated transistors with reduced impedance difference

Semiconductor fabrication process including an SiGe rework method

GLOBALFOUNDRIES SG PTE LTD

Method of manufacture of an integrated circuit system with self-aligned isolation structures

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Memory cell structure and method for fabrication thereof

Integrated circuit having a plurality of MOSFET devices

IBM

Method and apparatus for post silicide spacer removal

Dislocation engineering using a scanned laser

Dislocation engineering using a scanned laser

TEO LEE WEE

Capacitor top plate over source/drain to form a 1T memory device

Hybrid orientation substrate with stress layer

INFINEON TECHNOLOGIES AG

Methods of manufacturing semiconductor devices and structures thereof

SAMSUNG ELECTRONICS CO LTD

Stress optimization in dual embedded epitaxially grown semiconductor processing

LEE YONG MENG

Spacer-less low-K dielectric processes

YANG JONG HO

Methods of forming p-channel field effect transistors having SiGe source/drain regions

MISHRA SHAILENDRA

Method of forming shallow trench isolation structures for integrated circuits

LAI CHUNG WOH

Dislocation engineering using a scanned laser

WIDODO JOHNNY

Nested and isolated transistors with reduced impedance difference