Inventor

WIDODO JOHNNY

SG21 patents

⚠️ This page may combine multiple inventors who share the name “WIDODO JOHNNY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WIDODO JOHNNY

CHARTERED SEMICONDUCTOR MFG

Entire encapsulation of Cu interconnects using self-aligned CuSiN film

Method and apparatus for providing void structures

Semiconductor processing system with ultra low-K dielectric

Integrated circuit system employing selective epitaxial growth technology

Nested and isolated transistors with reduced impedance difference

Integrated circuit having ultralow-K dielectric layer

SAMSUNG ELECTRONICS CO LTD

Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon

Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques

Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein

Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall

Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby

Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses

GLOBALFOUNDRIES SG PTE LTD

Method of manufacture of an integrated circuit system with self-aligned isolation structures

Memory cell structure and method for fabrication thereof

Method of controlled low-k via etch for Cu interconnections

Integrated circuit having a plurality of MOSFET devices

TEO LEE WEE

Capacitor top plate over source/drain to form a 1T memory device

Hybrid orientation substrate with stress layer

IBM

BEOL interconnect structures with improved resistance to stress

MISHRA SHAILENDRA

Method of forming shallow trench isolation structures for integrated circuits

WIDODO JOHNNY

Nested and isolated transistors with reduced impedance difference