Inventor

STEINMACHER-BUROW BURKHARD

DE60 patents

⚠️ This page may combine multiple inventors who share the name “STEINMACHER-BUROW BURKHARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEINMACHER-BUROW BURKHARD

IBM

Cache line states identifying memory cache

Address layout over physical memory

DMA engine for repeating communication patterns

Multiple node remote messaging

Address layout over physical memory

Conditional access with timeout

Cache management directory where hardware manages cache write requests and software manages cache read requests

Coalescing messages using a network interface controller

Accessing an N-way linked list

Computer system with groups of processor boards

Reader-writer lock

Re-utilizing partially failed resources as network resources

Multi-input and binary reproducible, high bandwidth floating point adder in a collective network

Error recovery to enable error-free message transfer between nodes of a computer network

Deadlock-free class routes for collective communications embedded in a multi-dimensional torus network

Server recovery from a change in storage control chip

Server recovery from a change in storage control chip

Virtual drawers in a server

Accessing an N-way linked list

Uniform memory access architecture

Message passing with queues and channels

Partial computer processor core shutoff

Coordination of cache memory operations

Embedding global barrier and collective in a torus network

Uniform memory access architecture

Coalescing messages using a network interface controller

Coalescing messages using a network interface controller

Data processing system with main and balcony boards

Reader-writer lock

Computer system with groups of processor boards

Atomic memory operations on an N-way linked list

Embedding global and collective in a torus network with message class map based tree path selection

Atomic memory operations on an N-way linked list

Concurrent array-based queue

CHEN DONG

Distributed parallel messaging for multiprocessor systems

Multi-input and binary reproducible, high bandwidth floating point adder in a collective network

Optimizing TLB entries for mixed page size storage in contiguous memory

Optimizing TLB entries for mixed page size storage in contiguous memory

Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded, fetch-and-decrement-bounded and store-on-twin synchronization primitives

Remote processing and memory utilization

Store-operate-coherence-on-value

Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders

Implementing asyncronous collective operations in a multi-node processing system

GLOBALFOUNDRIES INC

Multi-petascale highly efficient parallel supercomputer

Multiple core processing with high throughput atomic memory operations

BLUMRICH MATTHIAS A

Cache as point of coherence in multiprocessor system

Local rollback for fault-tolerance in parallel computing systems

ASAAD SAMEH

Multi-petascale highly efficient parallel supercomputer

BELLOFATTO RALPH A

Reproducibility in a multiprocessor system

GOODING THOMAS M

Heap/stack guard pages using a wakeup unit