Inventor

SUNG CHIAKANG

US194 patents

⚠️ This page may combine multiple inventors who share the name “SUNG CHIAKANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUNG CHIAKANG

ALTERA CORP

Programmable I/O element circuit for high speed logic devices

Programmable logic integrated circuit devices with low voltage differential signaling capabilities

Programmable logic array integrated circuit devices with interleaved logic array blocks

I/O duty cycle and skew control

On-chip termination with calibrated driver strength

Programmable logic integrated circuit devices with differential signaling capabilities

Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit

LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device

Programmable wide-range frequency synthesizer

Logic region resources for programmable logic devices

Programmable logic device architectures

Programmable logic array integrated circuits

Method and apparatus for securing programming data of a programmable logic device

Variable depth and width memory device

Programmable low-voltage differential signaling output driver

Programmable high speed I/O interface

On/off reference voltage switch for multiple I/O standards

Programmable high speed I/O interface

Input buffer for multiple differential I/O standards

Programmable phase shift circuitry

Dual-port SRAM in a programmable logic device

Systems and methods for on-chip impedance termination

Phase-locked loop circuitry for programmable logic devices

Phase-locked loop circuitry for programmable logic devices

Phase-locked loop or delay-locked loop circuitry for programmable logic devices

LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device

Programmable phase shift circuitry

Cascaded programming with multiple-purpose pins

Phase-locked loop circuitry for programmable logic devices

Phase-locked loop or delay-locked loop circuitry for programmable logic devices

Method and apparatus for securing programming data of programmable logic device

Read-leveling implementations for DDR3 applications on an FPGA

Techniques for programming programmable logic array devices

Clock edge de-skew

Techniques for providing multiple termination impedance values to pins on an integrated circuit

Control circuit for self-compensating delay chain for multiple-data-rate interfaces

High-performance memory interface circuit architecture

Programmable on-chip differential termination impedance

Self-compensating delay chain for multiple-date-rate interfaces

Multiple data rate interface architecture

PCI-compatible programmable logic devices

Loop circuitry with low-pass noise filter

Method and apparatus for protecting a circuit during a hot socket condition

Multiple data rate interface architecture

Programmable on-chip differential termination impedance

Schmitt trigger circuit with adjustable trip point voltages

Multiple data rate interface architecture

On-chip impedance matching circuit

WANG BONNIE I

Adjustable drive strength input-output buffer circuitry

On-die input reference voltage with self-calibrating duty cycle correction