Inventor

WANG BONNIE I

US87 patents

⚠️ This page may combine multiple inventors who share the name “WANG BONNIE I”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG BONNIE I

ALTERA CORP

Programmable logic integrated circuit devices with low voltage differential signaling capabilities

Programmable logic array integrated circuit devices with interleaved logic array blocks

Programmable logic integrated circuit devices with differential signaling capabilities

Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit

I/O cell configuration for multiple I/O standards

LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device

Programmable wide-range frequency synthesizer

Logic region resources for programmable logic devices

Programmable logic device architectures

Method and apparatus for securing programming data of a programmable logic device

Programmable high speed I/O interface

Programmable high speed I/O interface

Programmable phase shift circuitry

Systems and methods for on-chip impedance termination

Phase-locked loop circuitry for programmable logic devices

Phase-locked loop or delay-locked loop circuitry for programmable logic devices

LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device

Programmable phase shift circuitry

Phase-locked loop or delay-locked loop circuitry for programmable logic devices

Method and apparatus for securing programming data of programmable logic device

Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices

Clock edge de-skew

Programmable on-chip differential termination impedance

Self-compensating delay chain for multiple-date-rate interfaces

Multiple data rate interface architecture

PCI-compatible programmable logic devices

Multiple data rate interface architecture

Programmable on-chip differential termination impedance

Multiple data rate interface architecture

On-chip impedance matching circuit

Voltage, temperature, and process independent programmable phase shift for PLL

Programmable logic integrated circuit devices with low voltage differential signaling capabilities

Fast locking phase frequency detector

Programmable logic integrated circuit devices with low voltage differential signaling capabilities

Programmable logic array integrated circuit architectures

Techniques for on-chip termination

Phase-locked loop or delay-locked loop circuitry for programmable logic devices

Input-output buffer circuit with a gate bias generator

Input-output circuitry for integrated circuits

Dynamic termination-impedance control for bidirectional I/O pins

Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices

Phase-locked loop circuitry for programmable logic devices

Programmable phase shift circuitry

I/O cell configuration for multiple I/O standards

Programmable current booster for faster edge-rate output in high speed applications

Fast locking phase frequency detector

WANG BONNIE I

Adjustable drive strength input-output buffer circuitry

On-die input reference voltage with self-calibrating duty cycle correction

Programmable output buffer

WANG XIAOBAO

Input-output circuit and method of improving input-output signals