Inventor

LIU HSIEN-WEN

TW141 patents

⚠️ This page may combine multiple inventors who share the name “LIU HSIEN-WEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU HSIEN-WEN

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-chip wafer level packages and methods of forming the same

Wafer level package (WLP) and method for forming the same

Semiconductor package with dual sides of metal routing

Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing

Package structure and method for forming the same

Using metal-containing layer to reduce carrier shock in package formation

Integrated fan-out packages

Wafer level package (WLP) and method for forming the same

Integrated fan-out package on package structure and methods of forming same

Structure and formation method for chip package

Multi-chip packages and methods of forming the same

Multi-chip packages

Methods of forming multi-chip wafer level packages

Integrated fan-out packages

Wafer level package (WLP) and method for forming the same

Wafer level package (WLP) and method for forming the same

Using metal-containing layer to reduce carrier shock in package formation

Integrated circuit test method and structure thereof

Semiconductor package with dual sides of metal routing

Package structure

Integrated circuit test method and structure thereof

Structure and formation method for chip package

Package structure with buffer layer sandwiched between encapsulation layer and semiconductor substrate

Methods and systems for improving surface mount joinder

NANYA TECHNOLOGY CORP

Method of forming a bottle-shaped trench in a semiconductor substrate

Method of forming a shallow trench isolation in a semiconductor substrate

Semiconductor structure and method of making the same

Method of fabricating shallow trench isolation

Method of forming a bottle-shaped trench in a semiconductor substrate

Method of rounding the corner of a shallow trench isolation region

Method of fabricating crown capacitor

DRAM memory device adjustable refresh rate method to alleviate effects of row hammer events

Dram and method for accessing a dram

Self-aligned method for forming contact of device with reduced step height

DRAM and method of operating the same

Memory device and operating method thereof

DRAM and method for managing power thereof

DRAM and method for managing power thereof

Method for forming crack stop structure

Method to prevent electrical shorts between tungsten interconnects

CHINGIS TECHNOLOGY CORP

Nonvolatile memory solution using single-poly pFlash technology

Nonvolatile memory solution using single-poly pFlash technology

HO JAR-MING

Antifuse element for integrated circuit device

SHIH SHING-YIH

Method for increasing adhesion between polysilazane and silicon nitride

CHEN CHIH-HAO

Methods for molding integrated circuits

LEE TZUNG-HAN

Memory layout structure and memory structure

SERCOMM CORP

Patch antenna and wireless communication device using the same

LIN CHIH CHING

Method for via formation in a semiconductor device

LEE HSIU-CHUN

Method of forming a trench by a silicon-containing mask

LEE TZUNG HAN

Vertical transistor for random-access memory and manufacturing method thereof