Inventor
KUMAR PRATHIBA
IN19 patents
⚠️ This page may combine multiple inventors who share the name “KUMAR PRATHIBA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
9 patentsUS10528349B2Jan 7, 2020
Branch synthetic generation across multiple microarchitecture generations
IBM16 citations93
US9921836B2Mar 20, 2018
Branch synthetic generation across multiple microarchitecture generations
IBM3 citations72
US9519481B2Dec 13, 2016
Branch synthetic generation across multiple microarchitecture generations
IBM1 citations62
US8930760B2Jan 6, 2015
Validating cache coherency protocol within a processor
IBM2 citations61
US8892949B2Nov 18, 2014
Effective validation of execution units within a processor
IBM2 citations61
US9886274B2Feb 6, 2018
Branch synthetic generation across multiple microarchitecture generations
IBM0 citations51
US9542183B2Jan 10, 2017
Branch synthetic generation across multiple microarchitecture generations
IBM0 citations51
US9158640B2Oct 13, 2015
Tightly-coupled context-aware irritator thread creation for verification of microprocessors
IBM0 citations51
US9021281B2Apr 28, 2015
Run-time task-level dynamic energy management
IBM1 citations48
ALAPATI SANGRAM
5 patentsUS8838801B2Sep 16, 2014
Cloud optimization using workload analysis
ALAPATI SANGRAM21 citations89
US8914515B2Dec 16, 2014
Cloud optimization using workload analysis
ALAPATI SANGRAM15 citations80
US8667255B2Mar 4, 2014
Measuring runtime coverage of architectural events of a microprocessor
ALAPATI SANGRAM2 citations60
US8850266B2Sep 30, 2014
Effective validation of execution units within a processor
ALAPATI SANGRAM0 citations50
US8904208B2Dec 2, 2014
Run-time task-level dynamic energy management
ALAPATI SANGRAM0 citations47
KUMAR PRATHIBA
3 patentsUS8607243B2Dec 10, 2013
Dynamic operating system optimization in parallel computing
KUMAR PRATHIBA6 citations81
US9032375B2May 12, 2015
Performance bottleneck identification tool
KUMAR PRATHIBA3 citations60
US8140901B2Mar 20, 2012
Validation of processors using a self-generating test case framework
KUMAR PRATHIBA3 citations60