P

Inventor

VAN DYKE DON A

US22 patents
⚠️ This page may combine multiple inventors who share the name “VAN DYKE DON A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CRAY RESEARCH INC

9 patents
US5430884AJul 4, 1995

Scalar/vector processor

CRAY RESEARCH INC131 citations98
US5745721AApr 28, 1998

Partitioned addressing apparatus for vector/scalar registers

CRAY RESEARCH INC34 citations96
US5659706AAug 19, 1997

Vector/scalar processor with simultaneous processing and instruction cache filling

CRAY RESEARCH INC28 citations96
US5640524AJun 17, 1997

Method and apparatus for chaining vector instructions

CRAY RESEARCH INC41 citations96
US5623650AApr 22, 1997

Method of processing a sequence of conditional vector IF statements

CRAY RESEARCH INC28 citations92
US5544337AAug 6, 1996

Vector processor having registers for control by vector resisters

CRAY RESEARCH INC33 citations92
US5706490AJan 6, 1998

Method of processing conditional branch instructions in scalar/vector processor

CRAY RESEARCH INC15 citations82
US5717881AFeb 10, 1998

Data processing system for processing one and two parcel instructions

CRAY RESEARCH INC6 citations73
US5598547AJan 28, 1997

Vector processor having functional unit paths of differing pipeline lengths

CRAY RESEARCH INC14 citations73

SUPERCOMPUTER SYSTEMS LTD

4 patents
US5179702AJan 12, 1993

System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling

SUPERCOMPUTER SYSTEMS LTD637 citations97
US5175856ADec 29, 1992

Computer with integrated hierarchical representation (ihr) of program wherein ihr file is available for debugging and optimizing during target execution

SUPERCOMPUTER SYSTEMS LTD264 citations97
US5202975AApr 13, 1993

Method for optimizing instruction scheduling for a processor having multiple functional resources

SUPERCOMPUTER SYSTEMS LTD106 citations95
US5307478AApr 26, 1994

Method for inserting a path instruction during compliation of computer programs for processors having multiple functional units

SUPERCOMPUTER SYSTEMS LTD29 citations91

ADVANCED MICRO DEVICES INC

2 patents
US7661107B1Feb 9, 2010

Method and apparatus for dynamic allocation of processing resources

ADVANCED MICRO DEVICES INC195 citations99
US7987465B2Jul 26, 2011

Method and apparatus for dynamic allocation of processing resources

ADVANCED MICRO DEVICES INC1 citations62

INTEL CORP

2 patents
US10102380B2Oct 16, 2018

Method and apparatus to provide secure application execution

INTEL CORP4 citations72
US10885202B2Jan 5, 2021

Method and apparatus to provide secure application execution

INTEL CORP0 citations62

SILICON GRAPHICS INC

1 patent
US6195676B1Feb 27, 2001

Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes

SILICON GRAPHICS INC554 citations97

MCKEEN FRANCIS X

1 patent
US9087200B2Jul 21, 2015

Method and apparatus to provide secure application execution

MCKEEN FRANCIS X37 citations96

ATI INT SRL

1 patent
US6904515B1Jun 7, 2005

Multi-instruction set flag preservation apparatus and method

ATI INT SRL15 citations84

VAN DYKE DON A

1 patent
US8631261B2Jan 14, 2014

Context state management for processor feature sets

VAN DYKE DON A4 citations66

VAN DYKE KORBIN

1 patent
US8381223B2Feb 19, 2013

Method and apparatus for dynamic allocation of processing resources

VAN DYKE KORBIN3 citations57