Inventor

MUDGE TREVOR NIGEL

US34 patents

⚠️ This page may combine multiple inventors who share the name “MUDGE TREVOR NIGEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUDGE TREVOR NIGEL

ADVANCED RISC MACH LTD

Error detection and recovery within processing stages of an integrated circuit

Systematic and random error detection and recovery within processing stages of an integrated circuit

Performance counter for adding variable work increment value that is dependent upon clock frequency

Data retention latch provision within integrated circuits

Memory system having fast and slow data reading mechanisms

Performance level selection in a data processing system by combining a plurality of performance requests

Error recovery within integrated circuit

Error recovery within integrated circuit

Integrated circuit with error correction mechanisms to offset narrow tolerancing

Error recovery within integrated circuit

Error recovery within integrated circuit

UNIV MICHIGAN

Error detection and recovery within processing stages of an integrated circuit

Systematic and random error detection and recovery within processing stages of an integrated circuit

Performance level setting of a data processing system

Performance level selection in a data processing system using a plurality of performance request calculating algorithms

Random number generator

Memory system having fast and slow data reading mechanisms

SATPATHY SUDHIR KUMAR

Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry

Crossbar circuitry and method of operation of such crossbar circuitry

Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry

Crossbar circuitry and method of operation of such crossbar circuitry

Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry

FLAUTNER KRISZTIAN

Error recover within processing stages of an integrated circuit

Error recovery within processing stages of an integrated circuit

Error recovery within integrated circuit

UNIV MICHIGAN REGENTS

Single cycle arbitration within an interconnect

Apparatus and methods for generating a selection signal to perform an arbitration in a single cycle between multiple signal inputs having respective data to send

Data processing apparatus with memory rename table for mapping memory addresses to registers

MUDGE TREVOR NIGEL

Storage of data in data stores having some faulty storage locations

Storage of data in data stores having some faulty storage locations

DRESLINSKI JR RONALD GEORGE

Cache memory system for a data processing apparatus

BILES STUART DAVID

Contention management for a hardware transactional memory

ROBERTS DAVID ANDREW

Cache memory with power saving state

MANVILLE DAVID THOMAS

Next branch table for use with a branch predictor