Inventor

LOU CHINE-GIE

TW73 patents

⚠️ This page may combine multiple inventors who share the name “LOU CHINE-GIE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LOU CHINE-GIE

TAIWAN SEMICONDUCTOR MFG

Method for forming a shallow trench isolation

Copper damascene manufacturing process

Method for forming copper dual damascene

Method of fabricating dual damascene structure

Method of manufacturing a deep trench capacitor

Three dimensional IC device and alignment methods of IC device substrates

Method of forming a metal insulator metal capacitor structure

Low thermal budget method for forming MIM capacitor

Method for forming a via and interconnect in dual damascene

Method of forming a DRAM capacitor structure including increasing the surface area using a discrete silicon mask

Fabrication method for a dual damascene structure

Method of forming shallow trench isolation structure

Method for manufacturing stacked capacitor

Method of forming dual damascene structure

Automatically adjustable wafer probe card

Method for forming salicide process

Method of planarizing inter-metal dielectric layer

Interconnect structure and method of fabricating same

Method of forming a dual damascene structure including smoothing the top part of a via

Method of manufacturing DRAM capacitor

Method for forming inter metal dielectric

Method of fabricating integrated circuits

Fabrication method for a double-side double-crown stacked capacitor

WORLDWIDE SEMICONDUCTOR MFG

Method for manufacturing stacked capacitor

Process for fabricating capacitor

Method of forming a dram crown capacitor

Method for forming a capacitor of a DRAM cell

Interconnection lines for improving thermal conductivity in integrated circuits and method for fabricating the same

Method of forming a shallow trench isolation

Method for fabricating metal interconnect structure

Method of fabricating shallow trench insolation

Structure and fabricating method of stacked capacitor

Method of multi-exposure for improving photolithography resolution

WORLDWIDE SEMICONDUCTOR MANUFA

Method for making dual damascene contact

Method for making fin-trench structured DRAM capacitor

Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant

Method for forming a crown capacitor

Method for forming a dual damascene contact and interconnect

Method for forming a planar intermetal dielectric layer

Method and structure for a conductive and a dielectric layer

Dishing free process for shallow trench isolation

IND TECH RES INST

Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits

Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation

Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal process

Dual damascene CMP process with BPSG reflowed contact hole

Dual damascene process using selective W CVD

Method for fabricating cylindrical capacitor for a memory cell

Process for producing a stacked capacitor having polysilicon with optimum hemispherical grains

TAIWAN SEMICONDUCTOR MFG CORP

Interlayer dielectric planarization process

Method for forming a crown capacitor