Inventor

CHEN HSUEH-CHUNG

TW128 patents

⚠️ This page may combine multiple inventors who share the name “CHEN HSUEH-CHUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN HSUEH-CHUNG

IBM

Double self aligned via patterning

Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration

Contact area structure and method for manufacturing the same

Double self-aligned via patterning

Via CD controllable top via structure

Back-end-of-line single damascene top via spacer defined by pillar mandrels

Non volatile resistive memory logic device

Reversible resistive memory logic gate device

Barrier-free vertical interconnect structure

Interconnect structure

Metallization interconnect structure formation

Multiple patterning scheme integration with planarized cut patterning

Metal spacer self aligned multi-patterning integration

Stack viabar structures

Fully aligned semiconductor device with a skip-level via

Image transfer using EUV lithographic structure and double patterning process

Electrically conductive interconnect including via having increased contact surface area

Drive-in Mn before copper plating

Electrically conductive interconnect including via having increased contact surface area

STI region for small fin pitch in FinFET devices

UNITED MICROELECTRONICS CORP

Apparatus for controlling uniformity of polished material

Polishing pad for a chemical mechanical polishing process

Method for improving non-uniformity of chemical mechanical polishing by over coating

Physical vapor deposition device for forming a uniform metal layer on a semiconductor wafer

Method for forming three dimensional semiconductor structure and three dimensional capacitor

Chemical-mechanical polishing station with end-point monitoring device

Method for forming dual-damascene interconnect structure

Method for monitoring a semiconductor wafer in a chemical mechanical polishing process

Chemical-mechanical polishing method

Method for determining thickness of material layer and chemical mechanical polishing endpoint

Method of fabricating shallow trench isolation

Exhaust line of chemical-mechanical polisher

Chemical mechanical polishing apparatus for controlling slurry distribution

Method of determining real time removal rate for polishing

TAIWAN SEMICONDUCTOR MFG

Method and apparatus for enhanced CMP planarization using surrounded dummy design

Method for fabricating air gap for semiconductor device

Metal electrical fuse structure

Design structure for coupling noise prevention

Three dimensional IC device and alignment methods of IC device substrates

Interconnects with improved reliability

Interconnect structure and method of fabricating same

Semiconductor device

IND TECH RES INST

Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation

Dual damascene CMP process with BPSG reflowed contact hole

Dual damascene process using selective W CVD

Silicide glue layer for W-CVD plug application

Selective W CVD plug process with a RTA self-aligned W-silicide barrier layer

In situ method for CMP endpoint detection

INFINEON TECHNOLOGIES AG

Process for forming fusible links

GLOBALFOUNDRIES INC

Making an efuse