Inventor

KYE JONGWOOK

US88 patents

⚠️ This page may combine multiple inventors who share the name “KYE JONGWOOK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KYE JONGWOOK

GLOBALFOUNDRIES INC

Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules

Middle of-line architecture for dense library layout using M0 hand-shake

Cut mask aware contact enclosure rule for grating and cut patterning solution

Transistor contacts self-aligned in two dimensions

Double sidewall image transfer process

Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology

Methods for improving double patterning route efficiency

Methods, apparatus and system for a passthrough-based architecture

Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell

Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability

Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines

Self-aligned double patterning process for two dimensional patterns

MOL architecture enabling ultra-regular cross couple

Mask-aware routing and resulting device

Utilization of block-mask and cut-mask for forming metal routing in an IC device

Cross-coupling-based design using diffusion contact structures

Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology

Wide pin for improved circuit routing

Semiconductor devices having dielectric caps on contacts and related fabrication methods

Self-aligned double patterning via enclosure design

Standard cell connection for circuit routing

Integrated circuit structure including power rail and tapping wire with method of forming same

Structure with local contact for shorting a gate electrode to a source/drain region

Methods of design rule checking of circuit designs

Transistor contacts self-aligned two dimensions

Methods of generating circuit layouts that are to be manufactured using SADP routing techniques

Methods of generating circuit layouts using self-alligned double patterning (SADP) techniques

Wide pin for improved circuit routing

Self-aligned double patterning process for metal routing

Method and apparatus for assisted metal routing

Methods to utilize merged spacers for use in fin generation in tapered IC devices

Method and apparatus for modified cell architecture and the resulting device

ADVANCED MICRO DEVICES INC

Method and apparatus for reducing biological contamination in an immersion lithography system

Process for observing overlay errors on lithographic masks

Silylation process for forming contacts

Measurement method of Zernike coma aberration coefficient

Lithography contrast enhancement technique by varying focus with wavelength modulation

Phase grating focus monitor using overlay technique

Inspection system for the pupil of a lithographic tool

Optical proximity correction (OPC) technique to compensate for flare

Immersion lithographic process using a conforming immersion medium

Phase-shift-moiré focus monitor

RASHED MAHBUB

Semiconductor device with transistor local interconnects

Middle-of-the-line constructs using diffusion contact structures

WOO YOUNGTAG

Double sidewall image transfer process

MA YUANSHENG

Layout designs with via routing structures

(unassigned)

Pupil filtering for a lithographic tool

YUAN LEI

Methods of making jogged layout routings double patterning compliant

WANG YAN

Cross-coupling-based design using diffusion contact structures

ADVANCED MICRO DEVICES IN

Test structures for electrical linewidth measurement and processes for their formation