Inventor

PRALL KIRK

US94 patents

⚠️ This page may combine multiple inventors who share the name “PRALL KIRK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PRALL KIRK

MICRON TECHNOLOGY INC

Array of non-volatile sonos memory cells

Multi-state memory cell with asymmetric charge trapping

Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture

Method for forming a semiconductor connection with a top surface having an enlarged recess

Method of making a field effect transistor having an elevated source and an elevated drain

Method of forming titanium silicide and titanium by chemical vapor deposition

Semiconductor connection with a top surface having an enlarged recess

Method of forming contact plugs

High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS

Method of making a field effect transistor having an elevated source and an elevated drain

Reduced pitch laser redundancy fuse bank structure

Memory cell imprint avoidance

Method for forming polysilicon local interconnects

2F2 memory device system

Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture

Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation

Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus

Method for forming a semiconductor connection with a top surface having an enlarged recess

Methods of forming a contact having titanium silicide and titanium formed by chemical vapor deposition

Ion implantation with programmable energy, angle, and beam current

Apparatus having titanium silicide and titanium formed by chemical vapor deposition

Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening

Self-aligned contact plugs

Method for cleaning waste matter from the backside of a semiconductor wafer substrate

Field effect transistor assemblies and transistor gate block stacks

Semiconductor processing method of fabricating field effect transistors

Acceleration of etch selectivity for self-aligned contact

Method for cleaning waste matter from the backside of a semiconductor wafer substrate

Field effect transistor

Method of forming field effect transistors relative to a semiconductor substrate and field effect transistors produced according to the method

Self-aligned contact formation for semiconductor devices

Reduced pitch laser redundancy fuse bank structure

Reduced leakage DRAM storage unit

Memory cell imprint avoidance

Method for forming a floating gate memory with polysilicon local interconnects

Fabricating a 2F2 memory device with a horizontal floating gate

System including a memory device having a semiconductor connection with a top surface having an enlarged recess

Methods of forming a contact having titanium formed by chemical vapor deposition

Method for forming a semiconductor connection with a top surface having an enlarged recess

Semiconductor constructions comprising electrically conductive plugs having monocrystalline and polycrystalline silicon

Method for forming a semiconductor connection with a top surface having an enlarged recess

Field effect transistors comprising electrically conductive plugs having monocrystalline and polycrystalline silicon

Method of forming a resistor and integrated circuitry having a resistor construction

Multi-state memory cell with asymmetric charge trapping

Contactless uniform-tunneling separate p-well (cusp) non-volatile memory array architecture, fabrication and operation

Structure and method of fabricating a transistor having a trench gate

Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture

MICRON SEMICONDUCTOR INC

Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells

(unassigned)

Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors

ROUND ROCK RES LLC

Structure and method of fabricating a transistor having a trench gate