Inventor

LEVY SAGY

IL44 patents

⚠️ This page may combine multiple inventors who share the name “LEVY SAGY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEVY SAGY

POLISHCHUK IGOR

Memory transistor with multiple charge storing layers and a high work function gate electrode

Memory transistor with multiple charge storing layers and a high work function gate electrode

Nonvolatile charge trap memory device having a high dielectric constant blocking region

Memory transistor with multiple charge storing layers and a high work function gate electrode

Methods for fabricating semiconductor memory with process induced strain

Nonvolatile charge trap memory device having a high dielectric constant blocking region

Methods for fabricating semiconductor memory with process induced strain

RAMKUMAR KRISHNASWAMY

Method of fabricating a nonvolatile charge trap memory device

Radical oxidation process for fabricating a nonvolatile charge trap memory device

Method of fabricating a nonvolatile charge trap memory device

Integration of non-volatile charge trap memory devices and logic CMOS devices

Integration of non-volatile charge trap memory devices and logic CMOS devices

Sequential deposition and anneal of a dielectic layer in a charge trapping memory device

LEVY SAGY

Oxide-nitride-oxide stack having multiple oxynitride layers

Oxide-nitride-oxide stack having multiple oxynitride layers

Oxynitride bilayer formed using a precursor inducing a high charge trap density in a top layer of the bilayer

Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

Nitridation oxidation of tunneling layer for improved SONOS speed and retention

Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

CYPRESS SEMICONDUCTOR CORP

Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices

Trapped-charge non-volatile memory with uniform multilevel programming

Nonvolatile charge trap memory device having &lt;100&gt; crystal plane channel orientation

Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

Silicon nitride films

TOWER SEMICONDUCTOR LTD

Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure

Double RESURF LDMOS with separately patterned P+ and N+ buried layers formed by shared mask

Apparatus of a metal-oxide-semiconductor (MOS) transistor including a multi-split gate

Semiconductor die with a metal via

LDMOS device having a low angle sloped oxide

Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure

Longitude Flash Memory Solutions Ltd

Oxide-nitride-oxide stack having multiple oxynitride layers

Oxide-nitride-oxide stack having multiple oxynitride layers

Oxide-nitride-oxide stack having multiple oxynitride layers

MATTSON TECH INC

UV pretreatment process for ultra-thin oxynitride formation

Method of forming dielectric films

ASSOCIATES ISRAEL LTD AG

Selective hemispherical grain silicon deposition

Semiconductor wafer pretreatment utilizing ultraviolet activated chlorine

PUCHNER HELMUT

SONOS type stacks for nonvolatile change trap memory devices and methods to form the same

UNIV CALIFORNIA

Method for depositing a coating having a relatively high dielectric constant onto a substrate

KOUTNY JR WILLIAM W C

Integration of non-volatile charge trap memory devices and logic CMOS devices

CYPRESS SEMICONDUCTOR CORPORTI

Single-wafer process for fabricating a nonvolatile charge trap memory device

JENNE FREDRICK

SONOS ONO stack scaling

TOWER SEMICONDUCTORS LTD

Lateral diffused metal oxide semiconductor field effect (LDMOS) transistor and device having LDMOS transistors

Nonvolatile charge trap memory device having <100> crystal plane channel orientation