Inventor
Ravi Hari Anand
IN12 patents
Patents
12 patentsUS9767888B1Sep 19, 2017
Methods and devices for high-sensitivity memory interface receiver
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US12205673B1Jan 21, 2025
Read data strobe path having variation compensation and delay lines
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US10566046B1Feb 18, 2020
Protocol compliant high-speed DDR transmitter
CADENCE DESIGN SYSTEMS INC2 citations72
US11483185B1Oct 25, 2022
Hardware efficient decision feedback equalization training
CADENCE DESIGN SYSTEMS INC4 citations71
US11323296B1May 3, 2022
Decision feedback equalization training scheme for GDDR applications
CADENCE DESIGN SYSTEMS INC4 citations71
US10545895B1Jan 28, 2020
Auto-zeroing receiver for memory interface devices
CADENCE DESIGN SYSTEMS INC2 citations71
US11580048B1Feb 14, 2023
Reference voltage training scheme
CADENCE DESIGN SYSTEMS INC3 citations69
US12289111B1Apr 29, 2025
System and method using a fast settling accumulator
CADENCE DESIGN SYSTEMS INC0 citations60
US12183427B1Dec 31, 2024
System and method for write clock double data rate duty cycle correction
CADENCE DESIGN SYSTEMS INC1 citations60
US11979262B1May 7, 2024
Identifying and training floating tap for decision feedback equalization
CADENCE DESIGN SYSTEMS INC1 citations60
US12413213B1Sep 9, 2025
Efficient clocking structures for high-speed systems using hybrid digital delay lanes
CADENCE DESIGN SYSTEMS INC0 citations59
US12184286B1Dec 31, 2024
Clock duty cycle measurement
CADENCE DESIGN SYSTEMS INC0 citations47