P

Inventor

HUM HERBERT H

US21 patents
⚠️ This page may combine multiple inventors who share the name “HUM HERBERT H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

17 patents
US9626321B2Apr 18, 2017

High performance interconnect

INTEL CORP14 citations92
US6922745B2Jul 26, 2005

Method and apparatus for handling locks

INTEL CORP42 citations89
US12197357B2Jan 14, 2025

High performance interconnect

INTEL CORP2 citations85
US11741030B2Aug 29, 2023

High performance interconnect

INTEL CORP2 citations83
US10248591B2Apr 2, 2019

High performance interconnect

INTEL CORP5 citations83
US7721050B2May 18, 2010

Re-snoop for conflict resolution in a cache coherency protocol

INTEL CORP8 citations83
US7080209B2Jul 18, 2006

Method and apparatus for processing a load-lock instruction using a relaxed lock protocol

INTEL CORP10 citations73
US12189550B2Jan 7, 2025

High performance interconnect

INTEL CORP0 citations72
US11269793B2Mar 8, 2022

High performance interconnect

INTEL CORP0 citations72
US10725920B2Jul 28, 2020

Processors having virtually clustered cores and cache slices

INTEL CORP2 citations71
US10725919B2Jul 28, 2020

Processors having virtually clustered cores and cache slices

INTEL CORP1 citations71
US10705960B2Jul 7, 2020

Processors having virtually clustered cores and cache slices

INTEL CORP2 citations71
US11513957B2Nov 29, 2022

Processor and method implementing a cacheline demote machine instruction

INTEL CORP0 citations62
US10073779B2Sep 11, 2018

Processors having virtually clustered cores and cache slices

INTEL CORP1 citations61
US10817425B2Oct 27, 2020

Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads

INTEL CORP0 citations52
US8631210B2Jan 14, 2014

Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines

INTEL CORP0 citations50
US9436605B2Sep 6, 2016

Cache coherency apparatus and method minimizing memory writeback operations

INTEL CORP0 citations41

HUM HERBERT H

2 patents

LIU WEI

1 patent

MOGA ADRIAN C

1 patent