Inventor

VASH JAMES R

US19 patents

⚠️ This page may combine multiple inventors who share the name “VASH JAMES R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VASH JAMES R

INTEL CORP

Core snoop handling during performance state and power state transitions in a distributed caching agent

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline

Apparatus, system, and methods for facilitating one-way ordering of messages

Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline

VASH JAMES R

Apparatus, system, and methods for facilitating one-way ordering of messages

Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline

Inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline

Inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline

System-wide quiescence and per-thread transaction fence in a distributed caching agent

Retry based protocol with source/receiver FIFO recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction

Monitoring thread synchronization in a distributed cache

BHANDARU MALINI K

Dynamically controlling interconnect frequency in a processor

CHANG LUKE

Tunneling platform management messages through inter-processor interconnects

HUM HERBERT H

Directory cache supporting non-atomic input/output operations

NATU MAHESH S

Supporting advanced RAS features in a secured computing system