Inventor

MOGA ADRIAN C

US19 patents

⚠️ This page may combine multiple inventors who share the name “MOGA ADRIAN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOGA ADRIAN C

INTEL CORP

Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory

Integrated three-dimensional (3D) DRAM cache

Virtual shared cache mechanism in a processing device

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Processor and method implementing a cacheline demote machine instruction

Processors having virtually clustered cores and cache slices

Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads

Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines

System, apparatus, and method for scheduling metadata requests

Cache coherency apparatus and method minimizing memory writeback operations

IBM

Caching memory contents into cache partitions based on memory locations

Increased computer peripheral throughput by using data available withholding

Increased computer peripheral throughput by using data available withholding

HINTON GLENN

Apparatus, method, and system for implementing micro page tables

MOGA ADRIAN C

Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines

HINTON GLENN J

Obtaining data for redundant multithreading (RMT) execution

VARMA ANKUSH

Multi-processor computing system having fast processor response to cache agent request capacity limit warning