Inventor
WRIGHT KENNETH LEE
US28 patents
⚠️ This page may combine multiple inventors who share the name “WRIGHT KENNETH LEE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
22 patentsUS7194587B2Mar 20, 2007
Localized cache block flush instruction
IBM19 citations88
US6785773B2Aug 31, 2004
Verification of global coherence in a multi-node NUMA system
IBM33 citations87
US7409504B2Aug 5, 2008
Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response
IBM9 citations84
US7360067B2Apr 15, 2008
Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network
IBM9 citations84
US6920521B2Jul 19, 2005
Method and system of managing virtualized physical memory in a data processing system
IBM12 citations84
US6907494B2Jun 14, 2005
Method and system of managing virtualized physical memory in a memory controller and processor system
IBM13 citations84
US6904490B2Jun 7, 2005
Method and system of managing virtualized physical memory in a multi-processor system
IBM12 citations84
US7493417B2Feb 17, 2009
Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system
IBM7 citations74
US7017024B2Mar 21, 2006
Data processing system having no system memory
IBM10 citations74
US6643662B1Nov 4, 2003
Split bi-directional stack in a linear memory array
IBM12 citations72
US7243194B2Jul 10, 2007
Method to preserve ordering of read and write operations in a DMA system by delaying read access
IBM8 citations71
US6473772B1Oct 29, 2002
Apparatus and methods for dynamic simulation event triggering
IBM13 citations71
US7359932B2Apr 15, 2008
Method and data processing system for microprocessor communication in a cluster-based multi-processor system
IBM2 citations63
US7356568B2Apr 8, 2008
Method, processing unit and data processing system for microprocessor communication in a multi-processor system
IBM5 citations63
US7284097B2Oct 16, 2007
Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes
IBM5 citations63
US6934825B1Aug 23, 2005
Bi-directional stack in a linear memory array
IBM5 citations61
US6629228B1Sep 30, 2003
Proportionally growing stack in a linear memory array
IBM4 citations61
US6795878B2Sep 21, 2004
Verifying cumulative ordering of memory instructions
IBM4 citations60
US7818364B2Oct 19, 2010
Method and data processing system for microprocessor communication in a cluster-based multi-processor system
IBM0 citations52
US7734877B2Jun 8, 2010
Method and data processing system for processor-to-processor communication in a clustered multi-processor system
IBM0 citations52
US7698373B2Apr 13, 2010
Method, processing unit and data processing system for microprocessor communication in a multi-processor system
IBM0 citations52
US7370155B2May 6, 2008
Chained cache coherency states for sequential homogeneous access to a cache line with outstanding data response
IBM0 citations42
RAMBUS INC
6 patentsUS11309015B2Apr 19, 2022
Floating body DRAM with reduced access energy
RAMBUS INC2 citations73
US10762010B2Sep 1, 2020
Multi-mode memory module and memory component
RAMBUS INC2 citations73
US11947474B2Apr 2, 2024
Multi-mode memory module and memory component
RAMBUS INC0 citations62
US11804259B2Oct 31, 2023
Floating body dram with reduced access energy
RAMBUS INC0 citations62
US11379392B2Jul 5, 2022
Multi-mode memory module and memory component
RAMBUS INC0 citations62
US10762948B2Sep 1, 2020
Floating body DRAM with reduced access energy
RAMBUS INC0 citations52