Inventor

LEE VICTOR W

US41 patents

⚠️ This page may combine multiple inventors who share the name “LEE VICTOR W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE VICTOR W

INTEL CORP

Performing power management in a multicore processor

Functional testing of logic circuits that use high-speed links

Instruction and logic to provide pushing buffer copy and store functionality

Loop vectorization methods and apparatus

Gather and scatter operations in multi-level memory hierarchy

Dynamically updating a power management policy of a processor

Performing power management in a multicore processor

Loop vectorization methods and apparatus

High performance persistent memory for region-centric consistent and atomic updates

Instruction to reduce elements in a vector register with strided access pattern

Pipeline circuit architecture to provide in-memory computation functionality

Performing power management in a multicore processor

Gather and scatter operations in multi-level memory hierarchy

Negotiable exchange of link layer functional parameters in electronic systems having components interconnected by a point-to-point network

Technique to perform concurrent updates to a shared data structure

System for flexible and negotiable exchange of link layer functional parameters

Instruction and logic to provide pushing buffer copy and store functionality

Processor with architecturally-visible programmable on-die storage to store data that is accessible by instruction

Method and system for flexible and negotiable exchange of link layer functional parameters

Dynamic interconnect width reduction to improve interconnect availability

Retraining derived clock receivers

Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate

Technologies for low-level composable high performance computing libraries

Texture unit for general purpose computing

Instructions for manipulating a multi-bit predicate register for predicating instruction sequences

LEE VICTOR W

Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate

Method and apparatus for attaching and detaching two utensils

Texture unit for general purpose computing

Grouping pixels to be textured

BHARADWAJ JAYASHANKAR

Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register

Speculative non-faulting loads and gathers

Apparatus and method for vectorization with speculation support

HUGHES CHRISTOPHER J

Gather and scatter operations in multi-level memory hierarchy

Gather and scatter operations in multi-level memory hierarchy

SMELYANSKIY MIKHAIL

Mechanism for conflict detection using SIMD

Vector instructions to enable efficient synchronization and parallel reduction operations

CHHUGANI JATIN

System and method for memory bandwidth friendly sorting on multi-core architectures

ICC IND INC

Flame retardant polyolefins for molding applications

KIM DAEHYUN

Method and apparatus for stream buffer management instructions

UNIROYAL PLASTICS CO

Antistatic thermoplastic composition comprising a graft polymer, halogenated thermoplastic polymer and conductive carbon black

STRACOVSKY HENRY

Reliability support in memory systems without error correcting code support