Inventor
CATABAY WILBUR G
US64 patents
⚠️ This page may combine multiple inventors who share the name “CATABAY WILBUR G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
43 patentsUS6423628B1Jul 23, 2002
Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines
LSI LOGIC CORP218 citations99
US6204192B1Mar 20, 2001
Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures
LSI LOGIC CORP166 citations99
US6028015AFeb 22, 2000
Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption
LSI LOGIC CORP173 citations99
US6881664B2Apr 19, 2005
Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
LSI LOGIC CORP75 citations98
US6232658B1May 15, 2001
Process to prevent stress cracking of dielectric films on semiconductor wafers
LSI LOGIC CORP93 citations98
US5660682AAug 26, 1997
Plasma clean with hydrogen gas
LSI LOGIC CORP100 citations98
US5933757AAug 3, 1999
Etch process selective to cobalt silicide for formation of integrated circuit structures
LSI LOGIC CORP265 citations97
US6727177B1Apr 27, 2004
Multi-step process for forming a barrier film for use in copper layer formation
LSI LOGIC CORP58 citations96
US6537896B1Mar 25, 2003
Process for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric material
LSI LOGIC CORP71 citations96
US6423630B1Jul 23, 2002
Process for forming low K dielectric material between metal lines
LSI LOGIC CORP66 citations96
US6391795B1May 21, 2002
Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
LSI LOGIC CORP53 citations96
US6350700B1Feb 26, 2002
Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
LSI LOGIC CORP59 citations96
US5770520AJun 23, 1998
Method of making a barrier layer for via or contact opening of integrated circuit structure
LSI LOGIC CORP57 citations96
US5902129AMay 11, 1999
Process for forming improved cobalt silicide layer on integrated circuit structure using two capping layers
LSI LOGIC CORP87 citations95
US7276441B1Oct 2, 2007
Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
LSI LOGIC CORP20 citations93
US6875693B1Apr 5, 2005
Via and metal line interface capable of reducing the incidence of electro-migration induced voids
LSI LOGIC CORP21 citations93
US6528423B1Mar 4, 2003
Process for forming composite of barrier layers of dielectric material to inhibit migration of copper from copper metal interconnect of integrated circuit structure into adjacent layer of low k dielectric material
LSI LOGIC CORP48 citations93
US6492731B1Dec 10, 2002
Composite low dielectric constant film for integrated circuit structure
LSI LOGIC CORP27 citations93
US5994775ANov 30, 1999
Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same
LSI LOGIC CORP39 citations93
US5956613ASep 21, 1999
Method for improvement of TiN CVD film quality
LSI LOGIC CORP27 citations93
US6939800B1Sep 6, 2005
Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures
LSI LOGIC CORP30 citations92
US6812134B1Nov 2, 2004
Dual layer barrier film techniques to prevent resist poisoning
LSI LOGIC CORP19 citations92
US6774057B1Aug 10, 2004
Method and structure for forming dielectric layers having reduced dielectric constants
LSI LOGIC CORP22 citations92
US6756674B1Jun 29, 2004
Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same
LSI LOGIC CORP36 citations92
US6503840B2Jan 7, 2003
Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning
LSI LOGIC CORP40 citations92
US6368979B1Apr 9, 2002
Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
LSI LOGIC CORP52 citations92
US6346490B1Feb 12, 2002
Process for treating damaged surfaces of low k carbon doped silicon oxide dielectric material after plasma etching and plasma cleaning steps
LSI LOGIC CORP53 citations92
US6297555B1Oct 2, 2001
Method to obtain a low resistivity and conformity chemical vapor deposition titanium film
LSI LOGIC CORP22 citations92
US5895267AApr 20, 1999
Method to obtain a low resistivity and conformity chemical vapor deposition titanium film
LSI LOGIC CORP20 citations92
US6686272B1Feb 3, 2004
Anti-reflective coatings for use at 248 nm and 193 nm
LSI LOGIC CORP20 citations91
US5789028AAug 4, 1998
Method for eliminating peeling at end of semiconductor substrate in metal organic chemical vapor deposition of titanium nitride
LSI LOGIC CORP17 citations84
US6858531B1Feb 22, 2005
Electro chemical mechanical polishing method
LSI LOGIC CORP13 citations83
US6930056B1Aug 16, 2005
Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure
LSI LOGIC CORP10 citations74
US6905909B2Jun 14, 2005
Ultra low dielectric constant thin film
LSI LOGIC CORP7 citations74
US6800940B2Oct 5, 2004
Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
LSI LOGIC CORP12 citations74
US6790784B2Sep 14, 2004
Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for intergrated circuit structure
LSI LOGIC CORP12 citations74
US6734560B2May 11, 2004
Diamond barrier layer
LSI LOGIC CORP6 citations74
US6613665B1Sep 2, 2003
Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface
LSI LOGIC CORP7 citations74
US6472314B1Oct 29, 2002
Diamond barrier layer
LSI LOGIC CORP12 citations74
US6884720B1Apr 26, 2005
Forming copper interconnects with Sn coatings
LSI LOGIC CORP6 citations73
US6777807B1Aug 17, 2004
Interconnect integration
LSI LOGIC CORP7 citations73
US5635244AJun 3, 1997
Method of forming a layer of material on a wafer
LSI LOGIC CORP16 citations72
US8043968B2Oct 25, 2011
Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
LSI LOGIC CORP3 citations63
LSI CORP
7 patentsUS7427563B2Sep 23, 2008
Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures
LSI CORP9 citations84
US7413984B2Aug 19, 2008
Multi-step process for forming a barrier film for use in copper layer formation
LSI CORP6 citations74
US7229923B2Jun 12, 2007
Multi-step process for forming a barrier film for use in copper layer formation
LSI CORP9 citations74
US7393780B2Jul 1, 2008
Dual layer barrier film techniques to prevent resist poisoning
LSI CORP7 citations73
US7285145B1Oct 23, 2007
Electro chemical mechanical polishing method and device for planarizing semiconductor surfaces
LSI CORP7 citations73
US7728433B2Jun 1, 2010
Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
LSI CORP1 citations63
US7220362B2May 22, 2007
Planarization with reduced dishing
LSI CORP2 citations63
Showing the top 50 of 64 patents by PatentIndex Score.