Inventor

NGO MINH VAN

US275 patents

⚠️ This page may combine multiple inventors who share the name “NGO MINH VAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NGO MINH VAN

ADVANCED MICRO DEVICES INC

Preparation of composite high-K/standard-K dielectrics for semiconductor devices

Methods for improving carrier mobility of PMOS and NMOS devices

Gate dielectric quality for replacement metal gate transistors

Implantation into high-K dielectric material after gate etch to facilitate removal

Method of forming copper sulfide for memory cell

Laser thermal annealing of silicon nitride for increased density and etch selectivity

Semiconductor memory with deuterated materials

Spin on polymers for organic memory devices

Conformal atomic liner layer in an integrated circuit interconnect

Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual

NH3/N2-plasma treatment to prevent organic ILD degradation

Copper interconnect with improved electromigration resistance

Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines

Process for reducing copper oxide during integrated circuit fabrication

Polymer memory device formed in via opening

Methods of forming passive layers in organic memory cells

Implantation for the formation of CuX layer in an organic memory device

Engineered metal gate electrode

Protection low-k ILD during damascene processing with thin liner

Nitrogen oxide plasma treatment for reduced nickel silicide bridging

Selective formation of top memory electrode by electroless formation of conductive materials

Method of forming reliable capped copper interconnects

Conformal barrier liner in an integrated circuit interconnect

Silane treatment of low dielectric constant materials in semiconductor device manufacturing

Gate array with multiple dielectric properties and method for forming same

Method of forming low resistance vias

H2-or H2/N2-plasma treatment to prevent organic ILD degradation

Nickel silicide process using starved silicon diffusion barrier

Method of forming reliable capped copper interconnects

Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface

Copper metalization with improved electromigration resistance

Method of forming reliable copper interconnects

Method of reliably capping copper interconnects

Method of reducing metal voidings in 0.25 μm AL interconnect

Reflowable-doped HDP film

Method for depositing silicon dioxide using low temperatures

Conformal barrier liner in an integrated circuit interconnect

Protection of low-k ILD during damascene processing with thin liner

Doped copper interconnects using laser thermal annealing

Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics

Interfacial barrier layer in semiconductor devices with high-K gate dielectric material

Barrier metal oxide interconnect cap in integrated circuits

Flash memory with controlled wordline width

Interconnects with improved barrier layer adhesion

Methods of forming capped copper interconnects with improved electromigration resistance

Interconnect methodology employing a low dielectric constant etch stop layer

Integrated plasma treatment and nickel deposition and tool for performing same

Use of sion for preventing copper contamination of dielectric layer

Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers

VANTIS CORP

Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration