Inventor

MERCHANT SAILESH MANSINH

US77 patents

⚠️ This page may combine multiple inventors who share the name “MERCHANT SAILESH MANSINH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MERCHANT SAILESH MANSINH

AGERE SYST GUARDIAN CORP

Integrated circuit device having dual damascene capacitor

Gate structure for integrated circuit fabrication

Microstructure control of copper interconnects

Multi-layered titanium nitride barrier structure

Silicon carbide barrier layers for porous low dielectric constant materials

Polishing pads from closed-cell elastomer foam

CMP system and slurry for polishing semiconductor wafers and related method

Methods of fabricating an integrated circuit device with composite oxide dielectric

Barrier for copper metallization

Method of making a capacitor

Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses

Chemical mechanical polishing composition and method of polishing metal layers using same

Method of making a graded grown, high quality oxide layer for a semiconductor device

CMP slurry for polishing semiconductor wafers and related methods

Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit

Technique for reducing dishing in Cu-based interconnects

Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit

Barrier for copper metallization

CMP system for polishing semiconductor wafers and related method

Colloidal suspension of abrasive particles containing magnesium as CMP slurry

High quality oxide for use in integrated circuits

Method of making a capacitor

AGERE SYSTEMS INC

Wire bonding method for copper interconnects in semiconductor devices

Inductor formed in an integrated circuit

Method and system for eliminating extrusions in semiconductor vias

Wire bonding to copper

Semiconductor device barrier layer

Structure and method for bonding to copper interconnect structures

Semiconductor device having reduced intra-level and inter-level capacitance

Copper silicide passivation for improved reliability

Method of forming in-situ electroplated oxide passivating film for corrosion inhibition

Reinforced bond pad

Capacitor for an integrated circuit

Structure and method for fabricating flip chip devices

Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics

LUCENT TECHNOLOGIES INC

Electronic mail alerting system and method with user options

Method for forming vias in a low dielectric constant material

Silicon IC contacts using composite TiN barrier layer

Silicon carbide barrier layers for porous low dielectric constant materials

Polycide gate structure with intermediate barrier

Layered silicon nitride deposition process

Titanium-tantalum barrier layer film and method for forming the same

Integrated circuit fabrication

Systems and methods for determining semiconductor wafer temperature and calibrating a vapor deposition device

Multilayered A1-alloy structure for metal conductors

Method of despositing an aluminum-rich layer

Method for cleaning via openings in integrated circuit manufacturing

Method for making an integrated circuit including deutrium annealing of metal interconnect layers

(unassigned)

Tungsten silicide nitride as an electrode for tantalum pentoxide devices

AGERE SYSTEM GUARDIAN CORP

Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method