Inventor

ROY PRADIP KUMAR

US66 patents

⚠️ This page may combine multiple inventors who share the name “ROY PRADIP KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROY PRADIP KUMAR

AGERE SYST GUARDIAN CORP

Integrated circuit device having dual damascene capacitor

Gate structure for integrated circuit fabrication

Local area alloying for preventing dishing of copper during chemical-mechanical polishing (CMP)

Microstructure control of copper interconnects

Multi-layered titanium nitride barrier structure

Silicon carbide barrier layers for porous low dielectric constant materials

Polishing pads from closed-cell elastomer foam

CMP system and slurry for polishing semiconductor wafers and related method

Methods of fabricating an integrated circuit device with composite oxide dielectric

Method for forming trench capacitors in SOI substrates

Method of making a capacitor

Chemical mechanical polishing composition and method of polishing metal layers using same

Method of making a graded grown, high quality oxide layer for a semiconductor device

CMP slurry for polishing semiconductor wafers and related methods

Technique for reducing dishing in Cu-based interconnects

CMP system for polishing semiconductor wafers and related method

Colloidal suspension of abrasive particles containing magnesium as CMP slurry

Thin film deposition of mixed metal oxides

High quality oxide for use in integrated circuits

Method of making a capacitor

Chemical mechanical polishing endpoint apparatus using component activity in effluent slurry

Integrated circuit capacitor including tapered plug

Integrated circuit capacitor including anchored plugs

LUCENT TECHNOLOGIES INC

Method for forming vias in a low dielectric constant material

Method for making an integrated circuit capacitor including tantalum pentoxide

Oxide/nitride stacked gate dielectric and associated methods

Silicon carbide barrier layers for porous low dielectric constant materials

Electrical parameter tester having decoupling means

Floating gate avalanche injection MOS transistors with high K dielectric control gates

Polycide gate structure with intermediate barrier

Layered silicon nitride deposition process

Titanium-tantalum barrier layer film and method for forming the same

Method of making integrated circuit capacitor including tapered plug

Method of making a dielectric for an integrated circuit

Semiconductor device fabrication

Multilayered A1-alloy structure for metal conductors

Chemical mechanical polishing endpoint detection by monitoring component activity in effluent slurry

Method for making an integrated circuit including deutrium annealing of metal interconnect layers

Integrated circuit fabrication

AGERE SYSTEMS INC

Pad for chemical mechanical polishing

Compound, high-K, gate and capacitor insulator layer

Two-step oxidation process for oxidizing a silicon substrate wherein the first step is carried out at a temperature below the viscoelastic temperature of silicon dioxide and the second step is carried out at a temperature above the viscoelastic temperature

Method of forming in-situ electroplated oxide passivating film for corrosion inhibition

Selective laser annealing of semiconductor material

Capacitor for an integrated circuit

Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer

Trench capacitors in SOI substrates

Process for making mixed metal oxides

(unassigned)

Tungsten silicide nitride as an electrode for tantalum pentoxide devices

AGERE SYSTEM GUARDIAN CORP

Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method