Inventor

KUO CHIEN-CHU

US3 patents

⚠️ This page may combine multiple inventors who share the name “KUO CHIEN-CHU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CADENCE DESIGN SYSTEMS INC

2 patents

US7926011B1Apr 12, 2011

System and method of generating hierarchical block-level timing constraints from chip-level timing constraints

CADENCE DESIGN SYSTEMS INC16 citations91

US7467367B1Dec 16, 2008

Method and system for clock tree synthesis of an integrated circuit

CADENCE DESIGN SYSTEMS INC28 citations87

LEVITSKY OLEG

1 patent

US8977994B1Mar 10, 2015

Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints

LEVITSKY OLEG4 citations66